/* * ---------------------------------------------------------------- * Copyright c Realtek Semiconductor Corporation, 2002 * All rights reserved. * * $Header: /home1/sub1/tmp/cvs2svn/skylark/skylark/skylark/linux-2.6.x/drivers/net/re865x/AsicDriver/rtl865xc_asicregs.h,v 1.3 2008-02-28 11:06:35 alva_zhang Exp $ * * Abstract: ASIC specific definitions. * * $Author: alva_zhang $ * * --------------------------------------------------------------- */ #ifndef _ASICREGS_H #define _ASICREGS_H /* * Just for check menuconfig .... */ #if defined(CONFIG_RTL_819X) #else #error You must choice either 865xB or 865xC in 'make menuconfig'. #endif #undef SWTABLE_NO_HW /* Basic features */ #ifdef CONFIG_RTL8196B #define MAX_PORT_NUMBER 5 #else #define MAX_PORT_NUMBER 6 #endif #define PORT_NUM_MASK 7 #define ALL_PORT_MASK 0x3F #define TABLE_ENTRY_DISTANCE (8 * sizeof(uint32)) #define SWTABLE_BASE_OF_ALL_TABLES 0xbb000000 #define table_access_addr_base(type) (SWTABLE_BASE_OF_ALL_TABLES + 0x10000 * (type)) /* Filtering Database features */ #define RTL865XC_FID_BITMASK 0x3 /* Register access macro (REG*()). */ #ifndef REG32 #define REG32(reg) (*((volatile uint32 *)(reg))) #endif #ifndef REG16 #define REG16(reg) (*((volatile uint16 *)(reg))) #endif #ifndef REG8 #define REG8(reg) (*((volatile uint8 *)(reg))) #endif /* Register access macro (READ_MEM32() and WRITE_MEM32()). */ #if defined(RTL865X_MODEL_USER)||defined(RTL865X_TEST) /* * big_endian() is a macro to make endian consistence between 865x board and x86 PC. * All the ASIC registers stored in memory will be stored at big-endian order. * Therefore, we will see the same result when memory dump ASIC registers. * * big_endian32() and big_endian16() are like ntohs() and ntohl(). * In order to reduce the complexity of include hirerachy, we don't use ntohs-related functions. */ #define big_endian32(x) ((((x)&0xff000000)>>24)|(((x)&0x00ff0000)>>8)|(((x)&0x0000ff00)<<8)|(((x)&0x000000ff)<<24)) #define big_endian16(x) (((x)>>8)|(((x)&0x000000ff)<<8)) #define big_endian(x) big_endian32(x) /* backward-compatible */ #else #define big_endian32(x) (x) #define big_endian16(x) (x) #define big_endian(x) big_endian32(x) /* backward-compatible */ #endif #if defined(RTL865X_MODEL_USER)||defined(RTL865X_MODEL_KERNEL) void WRITE_MEM32(uint32 reg, uint32 val); void WRITE_MEM16(uint32 reg, uint32 val); void WRITE_MEM8(uint32 reg, uint32 val); uint32 READ_MEM32(uint32 reg); uint32 READ_MEM16(uint32 reg); uint32 READ_MEM8(uint32 reg); void WRITE_VIR32(uint32 reg, uint32 val); void WRITE_VIR16(uint32 reg, uint32 val); void WRITE_VIR8(uint32 reg, uint32 val); uint32 READ_VIR32(uint32 reg); uint32 READ_VIR16(uint32 reg); uint32 READ_VIR8(uint32 reg); #else /* Target Platform, RTL865X_TEST */ #ifndef WRITE_MEM32 #define WRITE_MEM32(reg,val) REG32(reg)=big_endian(val) #endif #ifndef WRITE_MEM16 #define WRITE_MEM16(reg,val) REG16(reg)=big_endian16(val) #endif #ifndef WRITE_MEM8 #define WRITE_MEM8(reg,val) REG8(reg)=(val) #endif #ifndef READ_MEM32 #define READ_MEM32(reg) big_endian(REG32(reg)) #endif #ifndef READ_MEM16 #define READ_MEM16(reg) big_endian16(REG16(reg)) #endif #ifndef READ_MEM8 #define READ_MEM8(reg) (REG8(reg)) #endif #endif #ifdef CONFIG_RTL8196C_REVISION_B #define TOGGLE_BIT_IN_REG(reg, bit_shift) (WRITE_MEM32(reg, READ_MEM32(reg) ^ bit_shift)) #define TOGGLE_BIT_IN_REG_TWICE(reg, bit_shift) \ do{ \ TOGGLE_BIT_IN_REG(reg, bit_shift); \ TOGGLE_BIT_IN_REG(reg, bit_shift); \ } while (0) #else #define TOGGLE_BIT_IN_REG_TWICE(reg, bit_shift) #endif #define RTL_R32(addr) (*(volatile unsigned long *)(addr)) #define RTL_W32(addr, l) ((*(volatile unsigned long*)(addr)) = (l)) #define RTL_R8(addr) (*(volatile unsigned char*)(addr)) #define RTL_W8(addr, l) ((*(volatile unsigned char*)(addr)) = (l)) /* MACRO to update HW configuration */ #define UPDATE_MEM32(reg, val, mask, offset) \ do{ \ WRITE_MEM32( (reg), \ ((READ_MEM32(reg) & ~((mask) << (offset))) | (((val) & (mask)) << (offset))));\ } while (0) /* MACRO to get value of HW configuration */ #define GET_MEM32_VAL(reg, mask, offset) ((READ_MEM32(reg) >> (offset)) & (mask)) #define DIVISOR 1000 /* cfliu: change DIVISOR from 0xe to 4096 for watchdog */ /* yjlou: change DIVISOR from 4096 to 100 for better resolution. */ /* yjlou: change DIVISOR from 100 to 1000 for longer watchdog trigger. */ /* cfliu: change DIVISOR back to 4000 to let printk happy. */ #define REAL_SWCORE_BASE 0xBB800000 #define REAL_SYSTEM_BASE 0xB8000000 #define REAL_HSB_BASE 0xBB806280 #define REAL_HSA_BASE 0xBB806200 #define REAL_SWTBL_BASE 0xBB000000 #if defined(RTL865X_TEST) || defined(RTL865X_MODEL_USER) || defined(RTL865X_MODEL_KERNEL) #define VIRTUAL_SWCORE_REG_SIZE (1*64*1024) /* said, BB80_xxxx */ #define VIRTUAL_SYSTEM_REG_SIZE (2*64*1024) /* said, B800_xxxx */ #define VIRTUAL_SWCORE_TBL_SIZE (1*1024*1024+256*1024) /* said, BB00_xxxx */ extern int8 *pVirtualSWReg; extern int8 *pVirtualSysReg; extern int8 *pVirtualHsb; extern int8 *pVirtualHsa; extern int8 *pVirtualSWTable; #define SWCORE_BASE ((uint32)pVirtualSWReg) #define SWCORE_SIZE VIRTUAL_SWCORE_REG_SIZE #define SYSTEM_BASE ((uint32)pVirtualSysReg) #define SYSTEM_SIZE (VIRTUAL_SYSTEM_REG_SIZE) #define HSB_BASE ((uint32)pVirtualHsb) #define HSB_SIZE 0x40 #define HSA_BASE ((uint32)pVirtualHsa) #define HSA_SIZE 0x40 #else #define SWCORE_BASE REAL_SWCORE_BASE #define SYSTEM_BASE REAL_SYSTEM_BASE #define HSB_BASE REAL_HSB_BASE #define HSA_BASE REAL_HSA_BASE #endif #ifdef CONFIG_RTL_8198 #define PIN_MUX_SEL_2 (SYSTEM_BASE + 0x0044) #endif #ifndef REVR #define REVR (SYSTEM_BASE + 0x00000000) #endif #ifndef RTL8196C_REVISION_A #define RTL8196C_REVISION_A 0x80000001 #endif #ifndef RTL8196C_REVISION_B #define RTL8196C_REVISION_B 0x80000002 #endif /* Table access and CPU interface control registers */ #define TACI_BASE (SWCORE_BASE + 0x00004D00) #define SWTACR (0x000 + TACI_BASE) /* Table Access Control */ #define SWTASR (0x004 + TACI_BASE) /* Table Access Status */ #define SWTAA (0x008 + TACI_BASE) /* Table Access Address */ #define TCR0 (0x020 + TACI_BASE) /* Table Access Control 0 */ #define TCR1 (0x024 + TACI_BASE) /* Table Access Control 1 */ #define TCR2 (0x028 + TACI_BASE) /* Table Access Control 2 */ #define TCR3 (0x02C + TACI_BASE) /* Table Access Control 3 */ #define TCR4 (0x030 + TACI_BASE) /* Table Access Control 4 */ #define TCR5 (0x034 + TACI_BASE) /* Table Access Control 5 */ #define TCR6 (0x038 + TACI_BASE) /* Table Access Control 6 */ #define TCR7 (0x03C + TACI_BASE) /* Table Access Control 7 */ /* Table access control register field definitions */ #define ACTION_MASK 1 #define ACTION_DONE 0 #define ACTION_START 1 #define CMD_MASK (7 << 1) #define CMD_ADD (1 << 1) #define CMD_MODIFY (1 << 2) #define CMD_FORCE (1 << 3) #define STOP_TLU_READY (1<<19) #define EN_STOP_TLU (1<<18) /* Table access status register field definitions */ #define TABSTS_MASK 1 #define TABSTS_SUCCESS 0 #define TABSTS_FAIL 1 /* Vlan table access definitions */ #define STP_DISABLE 0 #define STP_BLOCK 1 #define STP_LEARN 2 #define STP_FORWARD 3 /* Protocol trapping table access definitions */ #define TYPE_TRAP_ETHERNET 0x00 #define TYPE_TRAP_IP 0x02 #define TYPE_TRAP_TCP 0x05 #define TYPE_TRAP_UDP 0x06 /* L3 Routing table access definitions */ #define PROCESS_PPPOE 0x00 #define PROCESS_DIRECT 0x01 #define PROCESS_INDIRECT 0x02 #define PROCESS_S_CPU 0x04 #define PROCESS_NXT_HOP 0x05 #define PROCESS_S_DROP 0x06 #define PROCESS_N_DROP 0x07 /* ACL table access definitions */ #define RULE_ETHERNET 0 #define RULE_IP 2 #define RULE_IFSEL 3 #define RULE_ICMP 4 #define RULE_IGMP 5 #define RULE_TCP 6 #define RULE_UDP 7 #define RULE_SRC_FILTER 8 #define RULE_DST_FILTER 9 #define ACTION_PERMIT 0 #define ACTION_REDIRECT 1 #define ACTION_S_DROP 2 #define ACTION_S_CPU 3 #define ACTION_N_DROP 4 #define ACTION_N_CPU 5 #define ACTION_CPU_FOR_LOGGING 5 #define ACTION_MIRROR 6 #define ACTION_PPPOE_REDIRECT 7 #define ACTION_DEFAULT_REDIRECT 8 #define ACTION_DEFAULT_MIRROR 9 #define ACTION_DROP_RATE_PPS 10 #define ACTION_LOG2CPU_RATE_PPS 11 #define ACTION_DROP_RATE_BPS 12 #define ACTION_LOG2CPU_RATE_BPS 13 /* MIB counter registers */ #define MIB_COUNTER_BASE (SWCORE_BASE + 0x00001000) #define MIB_CONTROL (0x00 + MIB_COUNTER_BASE) /*MIB control Register */ /* MIB counter registers */ #define MIB_ADDROFFSETBYPORT 0x80 /* Address offset of the same counters of each port. Ex: P0's ifInOctets counter and P1's ifInOctets counter. */ #define OFFSET_ETHERSTATSCPUEVENTPKT 0x84 #define OFFSET_IFINOCTETS_P0 0x100 #define OFFSET_IFINUCASTPKTS_P0 0x108 #define OFFSET_ETHERSTATSOCTETS_P0 0x10C #define OFFSET_ETHERSTATSUNDERSIZEPKTS_P0 0x114 #define OFFSET_ETHERSTATSFRAGMEMTS_P0 0x118 #define OFFSET_ETHERSTATSPKTS64OCTETS_P0 0x11C #define OFFSET_ETHERSTATSPKTS65TO127OCTETS_P0 0x120 #define OFFSET_ETHERSTATSPKTS128TO255OCTETS_P0 0x124 #define OFFSET_ETHERSTATSPKTS256TO511OCTETS_P0 0x128 #define OFFSET_ETHERSTATSPKTS512TO1023OCTETS_P0 0x12C #define OFFSET_ETHERSTATSPKTS1024TO1518OCTETS_P0 0x130 #define OFFSET_ETHERSTATSOVERSIZEPKTS_P0 0x134 #define OFFSET_ETHERSTATSJABBERS_P0 0x138 #define OFFSET_ETHERSTATSMULTICASTPKTS_P0 0x13C #define OFFSET_ETHERSTATSBROADCASTPKTS_P0 0x140 #define OFFSET_DOT1DTPPORTINDISCARDS_P0 0x144 #define OFFSET_ETHERSTATSDROPEVENTS_P0 0x148 #define OFFSET_DOT3STATSFCSERRORS_P0 0x14C #define OFFSET_DOT3STATSSYMBOLERRORS_P0 0x150 #define OFFSET_DOT3CONTROLINUNKNOWNOPCODES_P0 0x154 #define OFFSET_DOT3INPAUSEFRAMES_P0 0x158 #define OFFSET_IFOUTOCTETS_P0 0x800 #define OFFSET_IFOUTUCASTPKTS_P0 0x808 #define OFFSET_IFOUTMULTICASTPKTS_P0 0x80C #define OFFSET_IFOUTBROADCASTPKTS_P0 0x810 #define OFFSET_IFOUTDISCARDS 0x814 #define OFFSET_DOT3STATSSINGLECOLLISIONFRAMES_P0 0x818 #define OFFSET_DOT3STATSMULTIPLECOLLISIONFRAMES_P0 0x81C #define OFFSET_DOT3STATSDEFERREDTRANSMISSIONS_P0 0x820 #define OFFSET_DOT3STATSLATECOLLISIONS_P0 0x824 #define OFFSET_DOT3STATSEXCESSIVECOLLISIONS_P0 0x828 #define OFFSET_DOT3OUTPAUSEFRAMES_P0 0x82C #define OFFSET_DOT1DBASEPORTDELAYEXCEEDEDDISCARDS_P0 0x830 #define OFFSET_ETHERSTATSCOLLISIONS_P0 0x834 /* MIB control register field definitions */ #define ALL_COUNTER_RESTART_MASK 0x0007ffff /* SYS_COUNTER_RESTART | IN_COUNTER_RESTART_P8 | ... | OUT_COUNTER_RESTART_P0 */ #define SYS_COUNTER_RESTART (1 << 18) #define IN_COUNTER_RESTART_P8 (1 << 17) #define OUT_COUNTER_RESTART_P8 (1 << 16) #define IN_COUNTER_RESTART_P7 (1 << 15) #define OUT_COUNTER_RESTART_P7 (1 << 14) #define IN_COUNTER_RESTART_P6 (1 << 13) #define OUT_COUNTER_RESTART_P6 (1 << 12) #define IN_COUNTER_RESTART_P5 (1 << 11) #define OUT_COUNTER_RESTART_P5 (1 << 10) #define IN_COUNTER_RESTART_P4 (1 << 9) #define OUT_COUNTER_RESTART_P4 (1 << 8) #define IN_COUNTER_RESTART_P3 (1 << 7) #define OUT_COUNTER_RESTART_P3 (1 << 6) #define IN_COUNTER_RESTART_P2 (1 << 5) #define OUT_COUNTER_RESTART_P2 (1 << 4) #define IN_COUNTER_RESTART_P1 (1 << 3) #define OUT_COUNTER_RESTART_P1 (1 << 2) #define IN_COUNTER_RESTART_P0 (1 << 1) #define OUT_COUNTER_RESTART_P0 (1 << 0) #define PORT_FOR_COUNTING_OFFSET 24 /*8650 offset while 8650B offset is 21*/ #define CPU_EVENTS (0x074 + MIB_COUNTER_BASE) #define EXT_PORT_FOR_COUNTING_MASK 0x00E00000 #define EXT_PORT_FOR_COUNTING_OFFSET 21 #define RX_BYTES_1 (0x080 + MIB_COUNTER_BASE) #define RX_PKTS_1 (0x084 + MIB_COUNTER_BASE) #define DROP_EVENTS_1 (0x088 + MIB_COUNTER_BASE) #define CPU_EVENTS_1 (0x08C + MIB_COUNTER_BASE) #define RX_BYTES_2 (0x090 + MIB_COUNTER_BASE) #define RX_PKTS_2 (0x094 + MIB_COUNTER_BASE) #define DROP_EVENTS_2 (0x098 + MIB_COUNTER_BASE) #define CPU_EVENTS_2 (0x09C + MIB_COUNTER_BASE) #define TX_BYTES_1 (0x0A0 + MIB_COUNTER_BASE) #define TX_PKTS_1 (0x0A4 + MIB_COUNTER_BASE) #define TX_BYTES_2 (0x0A8 + MIB_COUNTER_BASE) #define TX_PKTS_2 (0x0AC + MIB_COUNTER_BASE) /* Pre-fetch control register */ #define PFBRst (1<<16) /* Pre-fetch buffer reset */ #define DFC_OV (1<<15) /* DFC counter overflow flag */ #define FPFHC_OV (1<<14) /* DPFHC counter overflow flag */ #define CDFC (1<<13) /* Clear Data Fetch Counter */ #define CDPFHC (1<<12) /* Clear Data Pre-Fetch Hit Counter */ #define EnDFC (1<<11) /* Enable Data Fetch Counter */ #define EnDPFHC (1<<10) /* Enable Data Pre-Fetch Hit Counter */ #define EnSDPreFetch_D_MASK (0x00000300) /* Enable SDRAM pre-fetch function for Data : Mask */ #define EnSDPreFetch_D_Disable (0x00000100) /* Enable SDRAM pre-fetch function for Data : disable */ #define EnSDPreFetch_D_4W (0x00000200) /* Enable SDRAM pre-fetch function for Data : 4W */ #define EnSDPreFetch_D_4W4W (0x00000300) /* Enable SDRAM pre-fetch function for Data : 4W+4W */ #define EnSDPreFetch_D_OFFSET (8) /* Enable SDRAM pre-fetch function for Data : Offset */ #define IFC_OV (1<<7) /* IFC counter overflow flag */ #define IPFHC_OV (1<<6) /* IPFHC counter overflow flag */ #define CIFC (1<<5) /* Clear Instruction Fetch Counter */ #define CIPFHC (1<<4) /* Clear Instruction Pre-Fetch Hit Counter */ #define EnIFC (1<<3) /* Enable Instruction Fetch Counter */ #define EnIPFHC (1<<2) /* Enable Instruction Pre-Fetch Hit Counter */ #define EnSDPreFetch_I_MASK (0x00000003) /* Enable SDRAM pre-fetch function for Instruction : Mask */ #define EnSDPreFetch_I_OFFSET (0) /* Enable SDRAM pre-fetch function for Instruction : Offset */ #define EnSDPreFetch_I_Disable (0x00000001) /* Enable SDRAM pre-fetch function for Instruction : disable */ #define EnSDPreFetch_I_4W (0x00000002) /* Enable SDRAM pre-fetch function for Instruction : 4W */ #define EnSDPreFetch_I_4W4W (0x00000003) /* Enable SDRAM pre-fetch function for Instruction : 4W+4W */ /* PHY control registers */ #define PHY_BASE (SWCORE_BASE + 0x00002000) #define PORT0_PHY_CONTROL (0x000 + PHY_BASE) #define PORT0_PHY_STATUS (0x004 + PHY_BASE) #define PORT0_PHY_IDENTIFIER_1 (0x008 + PHY_BASE) #define PORT0_PHY_IDENTIFIER_2 (0x00C + PHY_BASE) #define PORT0_PHY_AUTONEGO_ADVERTISEMENT (0x010 + PHY_BASE) #define PORT0_PHY_AUTONEGO_LINK_PARTNER_ABILITY (0x014 + PHY_BASE) #define PORT1_PHY_CONTROL (0x020 + PHY_BASE) #define PORT1_PHY_STATUS (0x024 + PHY_BASE) #define PORT1_PHY_IDENTIFIER_1 (0x028 + PHY_BASE) #define PORT1_PHY_IDENTIFIER_2 (0x02C + PHY_BASE) #define PORT1_PHY_AUTONEGO_ADVERTISEMENT (0x030 + PHY_BASE) #define PORT1_PHY_AUTONEGO_LINK_PARTNER_ABILITY (0x034 + PHY_BASE) #define PORT2_PHY_CONTROL (0x040 + PHY_BASE) #define PORT2_PHY_STATUS (0x044 + PHY_BASE) #define PORT2_PHY_IDENTIFIER_1 (0x048 + PHY_BASE) #define PORT2_PHY_IDENTIFIER_2 (0x04C + PHY_BASE) #define PORT2_PHY_AUTONEGO_ADVERTISEMENT (0x050 + PHY_BASE) #define PORT2_PHY_AUTONEGO_LINK_PARTNER_ABILITY (0x054 + PHY_BASE) #define PORT3_PHY_CONTROL (0x060 + PHY_BASE) #define PORT3_PHY_STATUS (0x064 + PHY_BASE) #define PORT3_PHY_IDENTIFIER_1 (0x068 + PHY_BASE) #define PORT3_PHY_IDENTIFIER_2 (0x06C + PHY_BASE) #define PORT3_PHY_AUTONEGO_ADVERTISEMENT (0x070 + PHY_BASE) #define PORT3_PHY_AUTONEGO_LINK_PARTNER_ABILITY (0x074 + PHY_BASE) #define PORT4_PHY_CONTROL (0x080 + PHY_BASE) #define PORT4_PHY_STATUS (0x084 + PHY_BASE) #define PORT4_PHY_IDENTIFIER_1 (0x088 + PHY_BASE) #define PORT4_PHY_IDENTIFIER_2 (0x08C + PHY_BASE) #define PORT4_PHY_AUTONEGO_ADVERTISEMENT (0x090 + PHY_BASE) #define PORT4_PHY_AUTONEGO_LINK_PARTNER_ABILITY (0x094 + PHY_BASE) #define PORT5_PHY_CONTROL (0x0A0 + PHY_BASE) #define PORT5_PHY_STATUS (0x0A4 + PHY_BASE) #define PORT5_PHY_IDENTIFIER_1 (0x0A8 + PHY_BASE) #define PORT5_PHY_IDENTIFIER_2 (0x0AC + PHY_BASE) #define PORT5_PHY_AUTONEGO_ADVERTISEMENT (0x0B0 + PHY_BASE) #define PORT5_PHY_AUTONEGO_LINK_PARTNER_ABILITY (0x0B4 + PHY_BASE) #define PORT6_PHY_CONTROL (0x0C0 + PHY_BASE) #define PORT6_PHY_STATUS (0x0C4 + PHY_BASE) #define PORT6_PHY_IDENTIFIER_1 (0x0C8 + PHY_BASE) #define PORT6_PHY_IDENTIFIER_2 (0x0CC + PHY_BASE) #define PORT6_PHY_AUTONEGO_ADVERTISEMENT (0x0D0 + PHY_BASE) #define PORT6_PHY_AUTONEGO_LINK_PARTNER_ABILITY (0x0D4 + PHY_BASE) /* PHY control register field definitions */ #define PHY_RESET (1 << 15) #define ENABLE_LOOPBACK (1 << 14) #define SPEED_SELECT_100M (1 << 13) #define SPEED_SELECT_10M 0 #define ENABLE_AUTONEGO (1 << 12) #define POWER_DOWN (1 << 11) #define ISOLATE_PHY (1 << 10) #define RESTART_AUTONEGO (1 << 9) #define SELECT_FULL_DUPLEX (1 << 8) #define SELECT_HALF_DUPLEX 0 #define SPEED_SELECT_1000M (1 << 6) /* PHY status register field definitions */ #define STS_CAPABLE_100BASE_T4 (1 << 15) #define STS_CAPABLE_100BASE_TX_FD (1 << 14) #define STS_CAPABLE_100BASE_TX_HD (1 << 13) #define STS_CAPABLE_10BASE_TX_FD (1 << 12) #define STS_CAPABLE_10BASE_TX_HD (1 << 11) #define STS_MF_PREAMBLE_SUPPRESSION (1 << 6) #define STS_AUTONEGO_COMPLETE (1 << 5) #define STS_REMOTE_FAULT (1 << 4) #define STS_CAPABLE_NWAY_AUTONEGO (1 << 3) #define STS_LINK_ESTABLISHED (1 << 2) #define STS_JABBER_DETECTED (1 << 1) #define STS_CAPABLE_EXTENDED (1 << 0) /* PHY identifier 1 */ #define OUT_3_18_MASK (0xFFFF << 16) #define OUT_3_18_OFFSET 16 #define OUT_19_24_MASK (0x3F << 10) #define OUT_19_24_OFFSET 10 #define MODEL_NUMBER_MASK (0x3F << 4) #define MODEL_NUMBER_OFFSET 4 #define REVISION_NUMBER_MASK 0x0F #define REVISION_NUMBER_OFFSET 0 /* PHY auto-negotiation advertisement and link partner ability registers field definitions */ #define NEXT_PAGE_ENABLED (1 << 15) #define ACKNOWLEDGE (1 << 14) #define REMOTE_FAULT (1 << 13) #define CAPABLE_PAUSE (1 << 10) #define CAPABLE_100BASE_T4 (1 << 9) #define CAPABLE_100BASE_TX_FD (1 << 8) #define CAPABLE_100BASE_TX_HD (1 << 7) #define CAPABLE_10BASE_TX_FD (1 << 6) #define CAPABLE_10BASE_TX_HD (1 << 5) #define SELECTOR_MASK 0x1F #define SELECTOR_OFFSET 0 #define CAP_100BASE_OFFSET 5 #define CAP_100BASE_MASK (0x1F << CAP_100BASE_OFFSET) /* 10/100 capability mask */ /* PHY 1000BASE-T control and 1000BASE-T Status */ #define CAPABLE_1000BASE_TX_FD (1 << 9) #define CAPABLE_1000BASE_TX_HD (1 << 8) #define ADVCAP_1000BASE_OFFSET 8 #define LPCAP_1000BASE_OFFSET 10 #define ADVCAP_1000BASE_MASK (0x3 << ADVCAP_1000BASE_OFFSET) /* advertisement capability mask */ #define LPCAP_1000BASE_MASK (0x3 << LPCAP_1000BASE_OFFSET) /* link partner status mask */ #define CPU_IFACE_BASE (SYSTEM_BASE+0x10000) /* 0xB8010000 */ #define CPUICR (0x000 + CPU_IFACE_BASE) /* Interface control */ #define CPURPDCR0 (0x004 + CPU_IFACE_BASE) /* Rx pkthdr descriptor control 0 */ #define CPURPDCR1 (0x008 + CPU_IFACE_BASE) /* Rx pkthdr descriptor control 1 */ #define CPURPDCR2 (0x00c + CPU_IFACE_BASE) /* Rx pkthdr descriptor control 2 */ #define CPURPDCR3 (0x010 + CPU_IFACE_BASE) /* Rx pkthdr descriptor control 3 */ #define CPURPDCR4 (0x014 + CPU_IFACE_BASE) /* Rx pkthdr descriptor control 4 */ #define CPURPDCR5 (0x018 + CPU_IFACE_BASE) /* Rx pkthdr descriptor control 5 */ #define CPURPDCR(idx) (CPURPDCR0 + (idx << 2)) /* Rx pkthdr descriptor control with index */ #define CPURMDCR0 (0x01c + CPU_IFACE_BASE) /* Rx mbuf descriptor control */ #define CPUTPDCR0 (0x020 + CPU_IFACE_BASE) /* Tx pkthdr descriptor control Low */ #define CPUTPDCR1 (0x024 + CPU_IFACE_BASE) /* Tx pkthdr descriptor control High */ #define CPUTPDCR(idx) (CPUTPDCR0 + (idx << 2)) /* Tx pkthdr descriptor control with index */ #define CPUIIMR (0x028 + CPU_IFACE_BASE) /* Interrupt mask control */ #define CPUIISR (0x02c + CPU_IFACE_BASE) /* Interrupt status control */ #define CPUQDM0 (0x030 + CPU_IFACE_BASE) /* Queue ID 0 and Descriptor Ring Mapping Register */ #define CPUQDM1 (0x032 + CPU_IFACE_BASE) /* Queue ID 1 and Descriptor Ring Mapping Register */ #define CPUQDM2 (0x034 + CPU_IFACE_BASE) /* Queue ID 2 and Descriptor Ring Mapping Register */ #define CPUQDM3 (0x036 + CPU_IFACE_BASE) /* Queue ID 3 and Descriptor Ring Mapping Register */ #define CPUQDM4 (0x038 + CPU_IFACE_BASE) /* Queue ID 4 and Descriptor Ring Mapping Register */ #define CPUQDM5 (0x03a + CPU_IFACE_BASE) /* Queue ID 5 and Descriptor Ring Mapping Register */ #define DMA_CR1 (0x040 + CPU_IFACE_BASE) /* DMA Control Register 1 */ #define DMA_CR2 (0x044 + CPU_IFACE_BASE) /* DMA Control Register 2 */ /* CPUICR - CPU interface control register field definitions */ #define TXCMD (1 << 31) /* Enable Tx */ #define RXCMD (1 << 30) /* Enable Rx */ #define BUSBURST_32WORDS 0 #define BUSBURST_64WORDS (1 << 28) #define BUSBURST_128WORDS (2 << 28) #define BUSBURST_256WORDS (3 << 28) #define MBUF_128BYTES 0 #define MBUF_256BYTES (1 << 24) #define MBUF_512BYTES (2 << 24) #define MBUF_1024BYTES (3 << 24) #define MBUF_2048BYTES (4 << 24) #define TXFD (1 << 23) /* Notify Tx descriptor fetch */ #define SOFTRST (1 << 22) /* Re-initialize all descriptors */ #define STOPTX (1 << 21) /* Stop Tx */ #define SWINTSET (1 << 20) /* Set software interrupt */ #define LBMODE (1 << 19) /* Loopback mode */ #define LB10MHZ (1 << 18) /* LB 10MHz */ #define LB100MHZ (1 << 18) /* LB 100MHz */ #define MITIGATION (1 << 17) /* Mitigation with timer1 */ #define EXCLUDE_CRC (1 << 16) /* Exclude CRC from length */ #define RX_SHIFT_OFFSET 0 /* CPU interface descriptor field defintions */ #define DESC_OWNED_BIT (1 << 0) #define DESC_RISC_OWNED (0 << 0) #define DESC_SWCORE_OWNED (1 << 0) #define DESC_WRAP (1 << 1) #define DESC_ENG_OWNED 1 /* CPUIIMR - CPU interface interrupt mask register field definitions */ #define LINK_CHANGE_IE (1 << 31) /* Link change interrupt enable */ #define RX_ERR_IE0 (1 << 25) /* Rx error interrupt enable for descriptor 0 */ #define RX_ERR_IE1 (1 << 26) /* Rx error interrupt enable for descriptor 1 */ #define RX_ERR_IE2 (1 << 27) /* Rx error interrupt enable for descriptor 2 */ #define RX_ERR_IE3 (1 << 28) /* Rx error interrupt enable for descriptor 3 */ #define RX_ERR_IE4 (1 << 29) /* Rx error interrupt enable for descriptor 4 */ #define RX_ERR_IE5 (1 << 30) /* Rx error interrupt enable for descriptor 5 */ #define RX_ERR_IE_ALL (0x3f<<25) /* Rx error interrupt enable for any descriptor */ #define TX_ERR_IE0 (1 << 23) /* Tx error interrupt pending for descriptor 0 */ #define TX_ERR_IE1 (1 << 24) /* Tx error interrupt pending for descriptor 1 */ #define TX_ERR_IE_ALL (0x3<<23) /* Tx error interrupt pending for any descriptor */ #define TX_ERR_IE (1 << 29) /* Tx error interrupt enable */ #define PKTHDR_DESC_RUNOUT_IE0 (1 << 17) /* Run out pkthdr descriptor 0 interrupt enable */ #define PKTHDR_DESC_RUNOUT_IE1 (1 << 18) /* Run out pkthdr descriptor 1 interrupt enable */ #define PKTHDR_DESC_RUNOUT_IE2 (1 << 19) /* Run out pkthdr descriptor 2 interrupt enable */ #define PKTHDR_DESC_RUNOUT_IE3 (1 << 20) /* Run out pkthdr descriptor 3 interrupt enable */ #define PKTHDR_DESC_RUNOUT_IE4 (1 << 21) /* Run out pkthdr descriptor 4 interrupt enable */ #define PKTHDR_DESC_RUNOUT_IE5 (1 << 22) /* Run out pkthdr descriptor 5 interrupt enable */ #define PKTHDR_DESC_RUNOUT_IE_ALL (0x3f << 17) /* Run out anyone pkthdr descriptor interrupt pending */ #define MBUF_DESC_RUNOUT_IE_ALL (1 << 11) /* Run out anyone mbuf interrupt pending */ #define MBUF_DESC_RUNOUT_IE0 (1 << 11) /* Run out mbuf descriptor 0 interrupt enable */ #define TX_DONE_IE0 (1 << 9) /* Tx Descript Ring 0 one packet done interrupt enable */ #define TX_DONE_IE1 (1 << 10) /* Tx Descript Ring 1 one packet done interrupt enable */ #define TX_DONE_IE_ALL (0x3 << 9) /* Any Tx Descript Ring one packet done interrupt enable */ #define RX_DONE_IE0 (1 << 3) /* Rx Descript Ring 0 one packet done interrupt enable */ #define RX_DONE_IE1 (1 << 4) /* Rx Descript Ring 1 one packet done interrupt enable */ #define RX_DONE_IE2 (1 << 5) /* Rx Descript Ring 2 one packet done interrupt enable */ #define RX_DONE_IE3 (1 << 6) /* Rx Descript Ring 3 one packet done interrupt enable */ #define RX_DONE_IE4 (1 << 7) /* Rx Descript Ring 4 one packet done interrupt enable */ #define RX_DONE_IE5 (1 << 8) /* Rx Descript Ring 5 one packet done interrupt enable */ #define RX_DONE_IE_ALL (0x3f << 3) /* Rx Descript Ring any one packet done interrupt enable */ #define TX_ALL_DONE_IE0 (1 << 1) /* Tx Descript Ring 0 all packets done interrupt enable */ #define TX_ALL_DONE_IE1 (1 << 2) /* Tx Descript Ring 1 all packets done interrupt enable */ #define TX_ALL_DONE_IE_ALL (0x3 << 1) /* Any Tx Descript Ring all packets done interrupt enable */ /* CPU interface interrupt status register field definitions */ #define LINK_CHANGE_IP (1 << 31) /* Link change interrupt pending */ #define RX_ERR_IP0 (1 << 25) /* Rx error descriptor 0 interrupt pending */ #define RX_ERR_IP1 (1 << 26) /* Rx error descriptor 1 interrupt pending */ #define RX_ERR_IP2 (1 << 27) /* Rx error descriptor 2 interrupt pending */ #define RX_ERR_IP3 (1 << 28) /* Rx error descriptor 3 interrupt pending */ #define RX_ERR_IP4 (1 << 29) /* Rx error descriptor 4 interrupt pending */ #define RX_ERR_IP5 (1 << 30) /* Rx error descriptor 5 interrupt pending */ #define RX_ERR_IP_ALL (0x3f<<25) /* Rx error any descriptor interrupt pending */ #define RX_ERR_IP(idx) (1 << (25+(idx))) /* Rx error descriptor [IDX] interrupt pending */ #define TX_ERR_IP0 (1 << 23) /* Tx error descriptor 0 interrupt pending */ #define TX_ERR_IP1 (1 << 24) /* Tx error descriptor 1 interrupt pending */ #define TX_ERR_IP_ALL (0x3<<23) /* Tx error any descriptor interrupt pending */ #define TX_ERR_IP(idx) (1 << (23+(idx))) /* Tx error descriptor [IDX] interrupt pending */ #define PKTHDR_DESC_RUNOUT_IP0 (1 << 17) /* Run out pkthdr descriptor 0 interrupt pending */ #define PKTHDR_DESC_RUNOUT_IP1 (1 << 18) /* Run out pkthdr descriptor 1 interrupt pending */ #define PKTHDR_DESC_RUNOUT_IP2 (1 << 19) /* Run out pkthdr descriptor 2 interrupt pending */ #define PKTHDR_DESC_RUNOUT_IP3 (1 << 20) /* Run out pkthdr descriptor 3 interrupt pending */ #define PKTHDR_DESC_RUNOUT_IP4 (1 << 21) /* Run out pkthdr descriptor 4 interrupt pending */ #define PKTHDR_DESC_RUNOUT_IP5 (1 << 22) /* Run out pkthdr descriptor 5 interrupt pending */ #define PKTHDR_DESC_RUNOUT_IP_ALL (0x3f << 17) /* Run out anyone pkthdr descriptor interrupt pending */ #define PKTHDR_DESC_RUNOUT_IP(idx) (1 << (17+(idx))) /* Run out pkthdr descriptor [IDX] interrupt pending */ #define MBUF_DESC_RUNOUT_IP_ALL (1 << 11) /* Run out anyone mbuf interrupt pending */ #define MBUF_DESC_RUNOUT_IP0 (1 << 11) /* Run out mbuf descriptor 0 interrupt pending */ #define TX_DONE_IP0 (1 << 9) /* Tx one packet done interrupt for descriptor 0 pending */ #define TX_DONE_IP1 (1 << 10) /* Tx one packet done interrupt for descriptor 1 pending */ #define TX_DONE_IP_ALL (0x3 << 9) /* Tx one packet done interrupt for any descriptor pending */ #define TX_DONE_IP(idx) (1 << (9+(idx))) /* Tx one packet done interrupt for descriptor [IDX] pending */ #define RX_DONE_IP0 (1 << 3) /* Rx one packet done 0 interrupt pending */ #define RX_DONE_IP1 (1 << 4) /* Rx one packet done 1 interrupt pending */ #define RX_DONE_IP2 (1 << 5) /* Rx one packet done 2 interrupt pending */ #define RX_DONE_IP3 (1 << 6) /* Rx one packet done 3 interrupt pending */ #define RX_DONE_IP4 (1 << 7) /* Rx one packet done 4 interrupt pending */ #define RX_DONE_IP5 (1 << 8) /* Rx one packet done 5 interrupt pending */ #define RX_DONE_IP_ALL (0x3f << 3) /* Rx one packet done anyone interrupt pending */ #define RX_DONE_IP(idx) (1 << (3+(idx))) /* Rx one packet done [IDX] interrupt pending */ #define TX_ALL_DONE_IP0 (1 << 1) /* Tx all packets done interrupt 0 pending */ #define TX_ALL_DONE_IP1 (1 << 2) /* Tx all packets done interrupt 1 pending */ #define TX_ALL_DONE_IP_ALL (0x03 << 1) /* Tx all packets done any interrupt pending */ #define TX_ALL_DONE_IP(idx) (1 << (1+(idx))) /* Tx all packets done interrupt [IDX] pending */ #define INTPENDING_NIC_MASK (RX_ERR_IP_ALL|TX_ERR_IP_ALL|RX_DONE_IP_ALL|PKTHDR_DESC_RUNOUT_IP_ALL) #define INTPENDING_RUN_OUT (PKTHDR_DESC_RUNOUT_IP_ALL) /* CPUQDM0,CPUQDM1,CPUQDM2,CPUQDM3,CPUQDM4,CPUQDM5 - Queue ID 0~5 and Descriptor Ring Mapping Register */ #define CPURxDesc_OFFSET 12 #define CPURxDesc_MASK (7<<12) #define Ext1RxDesc_OFFSET 8 #define Ext1RxDesc_MASK (7<<8) #define Ext2RxDesc_OFFSET 4 #define Ext2RxDesc_MASK (7<<4) #define Ext3RxDesc_OFFSET 0 #define Ext3RxDesc_MASK (7<<0) #define CPU_RX_DESC_SHIFT 12 #define EXT1_RX_DESC_SHIFT 8 #define EXT2_RX_DESC_SHIFT 4 #define EXT3_RX_DESC_SHIFT 0 /* Switch Core Control Registers */ #define SWCORECNR (SWCORE_BASE + 0x00006000) #define MACMR (0x004 + SWCORECNR) /* MAC monitor */ #define VLANTCR (0x008 + SWCORECNR) /* Vlan tag control */ #define DSCR0 (0x00C + SWCORECNR) /* Qos by DS control */ #define DSCR1 (0x010 + SWCORECNR) /* Qos by DS control */ #define QOSCR (0x014 + SWCORECNR) /* Qos control */ #if 0 /* phase out in 865xC */ #define SWTMCR (0x01C + SWCORECNR) /* Switch table misc control */ #endif #if 0 /* phase out in 865xC */ /* SWTMCR - Switch table misc control */ #define EN_BCAST (1<<30) /* Enable Broadcast Handling */ #define MCAST_TO_CPU (1<<29) /* Enable Multicast Table */ #define BRIDGE_PKT_TO_CPU (1<<27) /*802.1d packet to CPU*/ #define MCAST_PORT_EXT_MODE_OFFSET 5 /* Multicast port mode offset */ #define MCAST_PORT_EXT_MODE_MASK (0x3f << 5) /* Multicast port mode mask */ #define WAN_ROUTE_MASK (3 << 3) #define WAN_ROUTE_FORWARD (0 << 3) /* Route WAN packets */ #define WAN_ROUTE_TO_CPU (1 << 3) /* Forward WAN packets to CPU */ #define WAN_ROUTE_DROP (2 << 3) /* Drop WAN packets */ #endif /* Descriptor Diagnostic Register */ #define DESCDIAG_BASE (SWCORECNR + 0x0100) #define GDSR0 (DESCDIAG_BASE + 0x000) /* Global Descriptor Status Register 0 */ #define GDSR1 (DESCDIAG_BASE + 0x004) /* Global Descriptor Status Register 1 */ #define PCSR0 (DESCDIAG_BASE + 0x008) /* Port Congestion Status Register 0 */ #define PCSR1 (DESCDIAG_BASE + 0x00c) /* Port Congestion Status Register 1 */ #define P0_DCR0 (DESCDIAG_BASE + 0x010) /* Port 0 Descriptor Counter Register 0 */ #define P0_DCR1 (DESCDIAG_BASE + 0x014) /* Port 0 Descriptor Counter Register 1 */ #define P0_DCR2 (DESCDIAG_BASE + 0x018) /* Port 0 Descriptor Counter Register 2 */ #define P0_DCR3 (DESCDIAG_BASE + 0x01c) /* Port 0 Descriptor Counter Register 3 */ #define P1_DCR0 (DESCDIAG_BASE + 0x020) /* Port 1 Descriptor Counter Register 0 */ #define P1_DCR1 (DESCDIAG_BASE + 0x024) /* Port 1 Descriptor Counter Register 1 */ #define P1_DCR2 (DESCDIAG_BASE + 0x028) /* Port 1 Descriptor Counter Register 2 */ #define P1_DCR3 (DESCDIAG_BASE + 0x02c) /* Port 1 Descriptor Counter Register 3 */ #define P2_DCR0 (DESCDIAG_BASE + 0x030) /* Port 2 Descriptor Counter Register 0 */ #define P2_DCR1 (DESCDIAG_BASE + 0x034) /* Port 2 Descriptor Counter Register 1 */ #define P2_DCR2 (DESCDIAG_BASE + 0x038) /* Port 2 Descriptor Counter Register 2 */ #define P2_DCR3 (DESCDIAG_BASE + 0x03c) /* Port 2 Descriptor Counter Register 3 */ #define P3_DCR0 (DESCDIAG_BASE + 0x040) /* Port 3 Descriptor Counter Register 0 */ #define P3_DCR1 (DESCDIAG_BASE + 0x044) /* Port 3 Descriptor Counter Register 1 */ #define P3_DCR2 (DESCDIAG_BASE + 0x048) /* Port 3 Descriptor Counter Register 2 */ #define P3_DCR3 (DESCDIAG_BASE + 0x04c) /* Port 3 Descriptor Counter Register 3 */ #define P4_DCR0 (DESCDIAG_BASE + 0x050) /* Port 4 Descriptor Counter Register 0 */ #define P4_DCR1 (DESCDIAG_BASE + 0x054) /* Port 4 Descriptor Counter Register 1 */ #define P4_DCR2 (DESCDIAG_BASE + 0x058) /* Port 4 Descriptor Counter Register 2 */ #define P4_DCR3 (DESCDIAG_BASE + 0x05c) /* Port 4 Descriptor Counter Register 3 */ #define P5_DCR0 (DESCDIAG_BASE + 0x060) /* Port 5 Descriptor Counter Register 0 */ #define P5_DCR1 (DESCDIAG_BASE + 0x064) /* Port 5 Descriptor Counter Register 1 */ #define P5_DCR2 (DESCDIAG_BASE + 0x068) /* Port 5 Descriptor Counter Register 2 */ #define P5_DCR3 (DESCDIAG_BASE + 0x06c) /* Port 5 Descriptor Counter Register 3 */ #define P6_DCR0 (DESCDIAG_BASE + 0x070) /* Port CPU Descriptor Counter Register 0 */ #define P6_DCR1 (DESCDIAG_BASE + 0x074) /* Port CPU Descriptor Counter Register 1 */ #define P6_DCR2 (DESCDIAG_BASE + 0x078) /* Port CPU Descriptor Counter Register 2 */ #define P6_DCR3 (DESCDIAG_BASE + 0x07c) /* Port CPU Descriptor Counter Register 3 */ #define Pn_DSCR0(idx) (DESCDIAG_BASE + ((idx) * 0x10) + 0x010) #define Pn_DSCR1(idx) (DESCDIAG_BASE + ((idx) * 0x10) + 0x014) #define Pn_DSCR2(idx) (DESCDIAG_BASE + ((idx) * 0x10) + 0x018) #define Pn_DSCR3(idx) (DESCDIAG_BASE + ((idx) * 0x10) + 0x01c) #define Pn_IQDesCnt_OFFSET (0) #define Pn_IQDesCnt_MASK (0x3ff << Pn_IQDesCnt_OFFSET) #define Pn_OQDSCR_MASK (0x3ff)<> Pn_ODD_OQDSCR_OFFSET) & Pn_OQDSCR_MASK) : \ ((READ_MEM32(Pn_DSCR0(port)) >> Pn_EVEN_OQDSCR_OFFSET) & Pn_OQDSCR_MASK)): \ ((queue) == 2) || ((queue) == 3)? \ ((queue & 0x01)?((READ_MEM32(Pn_DSCR1(port)) >> Pn_ODD_OQDSCR_OFFSET) & Pn_OQDSCR_MASK) : \ ((READ_MEM32(Pn_DSCR1(port)) >> Pn_EVEN_OQDSCR_OFFSET) & Pn_OQDSCR_MASK)): \ ((queue) == 4) || ((queue) == 5)? \ ((queue & 0x01)?((READ_MEM32(Pn_DSCR2(port)) >> Pn_ODD_OQDSCR_OFFSET) & Pn_OQDSCR_MASK) : \ ((READ_MEM32(Pn_DSCR2(port)) >> Pn_EVEN_OQDSCR_OFFSET) & Pn_OQDSCR_MASK)): \ 0) #define Pn_IQDSCR(port) ((READ_MEM32(Pn_DSCR3(port)) & Pn_IQDesCnt_MASK) >> Pn_IQDesCnt_OFFSET) /* GDSR0 - Global Descriptor Status Register 0 */ #define DSCRUNOUT (1<<27) /* Descriptor Run Out */ #define TotalDscFctrl_Flag (1<<26) /* TotalDescriptor Flow Control event flag */ #define USEDDSC_OFFSET 16 /* Total Used Descriptor */ #define USEDDSC_MASK (0x3ff<<16) /* Total Used Descriptor */ #define SharedBufFCON_Flag (1<<14) /* SharedBufFCON threshold triggerred flag */ #define MaxUsedDsc_OFFSET 0 /* Max Used Descriptor Count History */ #define MaxUsedDsc_MASK (0x3ff<<0) /* Max Used Descriptor Count History */ /* PCSR0 - Port Congestion Status Register 0 */ #define P3OQCgst_OFFSET (24) #define P3OQCgst_MASK (0x7f << P3OQCgst_OFFSET) #define P2OQCgst_OFFSET (16) #define P2OQCgst_MASK (0x7f << P2OQCgst_OFFSET) #define P1OQCgst_OFFSET (8) #define P1OQCgst_MASK (0x7f << P1OQCgst_OFFSET) #define P0OQCgst_OFFSET (0) #define P0OQCgst_MASK (0x7f << P0OQCgst_OFFSET) #define P3QQCgst(queue) (((READ_MEM32(PCSR0) & P3OQCgst_MASK) >> P3OQCgst_OFFSET) & (1 << (queue))) #define P2QQCgst(queue) (((READ_MEM32(PCSR0) & P2OQCgst_MASK) >> P2OQCgst_OFFSET) & (1 << (queue))) #define P1QQCgst(queue) (((READ_MEM32(PCSR0) & P1OQCgst_MASK) >> P1OQCgst_OFFSET) & (1 << (queue))) #define P0QQCgst(queue) (((READ_MEM32(PCSR0) & P0OQCgst_MASK) >> P0OQCgst_OFFSET) & (1 << (queue))) /* PCSR1 - Port Congestion Status Register 1 */ #define IQCgst_OFFSET (24) #define IQCgst_MASK (0x7f << P3OQCgst_OFFSET) #define P6OQCgst_OFFSET (16) #define P6OQCgst_MASK (0x7f << P6OQCgst_OFFSET) #define P5OQCgst_OFFSET (8) #define P5OQCgst_MASK (0x7f << P5OQCgst_OFFSET) #define P4OQCgst_OFFSET (0) #define P4OQCgst_MASK (0x7f << P4OQCgst_OFFSET) #define IQCgst(port) (((READ_MEM32(PCSR1) & IQCgst_MASK) >> IQCgst_OFFSET) & (1 << (port))) #define P6QQCgst(queue) (((READ_MEM32(PCSR1) & P6OQCgst_MASK) >> P6OQCgst_OFFSET) & (1 << (queue))) #define P5QQCgst(queue) (((READ_MEM32(PCSR1) & P5OQCgst_MASK) >> P5OQCgst_OFFSET) & (1 << (queue))) #define P4QQCgst(queue) (((READ_MEM32(PCSR1) & P4OQCgst_MASK) >> P4OQCgst_OFFSET) & (1 << (queue))) #define TMCR (0x300 + SWCORECNR) /* Test mode control */ #if 1 /* According David Lu 2006/02/10 */ #define MIITM_TXR0 (0x400 + SWCORECNR) /* MAC Test Mode MII TX Interface Register */ #define MIITM_TXR1 (0x404 + SWCORECNR) /* MAC Test Mode MII TX Interface Register */ #define MIITM_RXR0 (0x408 + SWCORECNR) /* MAC Test Mode MII RX Interface Register */ #define MIITM_RXR1 (0x40C + SWCORECNR) /* MAC Test Mode MII RX Interface Register */ #define GMIITM_TXR0 (0x400 + SWCORECNR) /* MAC Test Mode MII TX Interface Register */ #define GMIITM_TXR1 (0x404 + SWCORECNR) /* MAC Test Mode MII TX Interface Register */ #define GMIITM_RXR0 (0x408 + SWCORECNR) /* MAC Test Mode MII RX Interface Register */ #define GMIITM_RXR1 (0x40C + SWCORECNR) /* MAC Test Mode MII RX Interface Register */ #else /* Before 2006/02/09 */ #define MIITM_TXR (0x400 + SWCORECNR) /* MAC Test Mode MII TX Interface Register */ #define MIITM_RXR (0x404 + SWCORECNR) /* MAC Test Mode MII RX Interface Register */ #endif #define EN_PHY_P4 (1 << 9) #define EN_PHY_P3 (1 << 8) #define EN_PHY_P2 (1 << 7) #define EN_PHY_P1 (1 << 6) #define EN_PHY_P0 (1 << 5) #define EN_FX_P4 (1 << 4) #define EN_FX_P3 (1 << 3) #define EN_FX_P2 (1 << 2) #define EN_FX_P1 (1 << 1) #define EN_FX_P0 (1 << 0) #define GUEST_VLAN_BITMASK 0xFFF #define MULTICAST_BROADCAST_BIT 0x1 #define PCRP_SIZE 4 #define STP_PortST 5 #define STP_PortST_BITMASK 3 /* MAC monitor register field definitions */ #define SYS_CLK_MASK (0x7 << 16) #define SYS_CLK_100M (0 << 16) #define SYS_CLK_90M (1 << 16) #define SYS_CLK_85M (2 << 16) #define SYS_CLK_96M (3 << 16) #define SYS_CLK_80M (4 << 16) #define SYS_CLK_75M (5 << 16) #define SYS_CLK_70M (6 << 16) #define SYS_CLK_50M (7 << 16) /* VLAN tag control register field definitions */ #define VLAN_TAG_ONLY (1 << 19) /* Only accept tagged packets */ #define MII_ENFORCE_MODE (1 << 4) /* Enable MII port property set by force mode */ /* Qos by DS control register */ /* Qos control register */ #define QWEIGHT_MASK (3 << 30) #define QWEIGHT_ALWAYS_H (3 << 30) /* Weighted round robin of priority always high first */ #define QWEIGHT_16TO1 (2 << 30) /* Weighted round robin of priority queue 16:1 */ #define QWEIGHT_8O1 (1 << 30) /* Weighted round robin of priority queue 8:1 */ #define QWEIGHT_4TO1 0 /* Weighted round robin of priority queue 4:1 */ #define EN_FCA_AUTOOFF (1 << 29) /* Enable flow control auto off */ #define DIS_DS_PRI (1 << 28) /* Disable DS priority */ #define DIS_VLAN_PRI (1 << 27) /* Disable 802.1p priority */ #define PORT5_H_PRI (1 << 26) /* Port 5 high priority */ #define PORT4_H_PRI (1 << 25) /* Port 4 high priority */ #define PORT3_H_PRI (1 << 24) /* Port 3 high priority */ #define PORT2_H_PRI (1 << 23) /* Port 2 high priority */ #define PORT1_H_PRI (1 << 22) /* Port 1 high priority */ #define PORT0_H_PRI (1 << 21) /* Port 0 high priority */ #define EN_QOS (1 << 20) /* Enable QoS */ /* Switch core misc control register field definitions */ #define DIS_P5_LOOPBACK (1 << 30) /* Disable port 5 loopback */ #define LINK_RGMII 0 /* RGMII mode */ #define LINK_MII_MAC 1 /* GMII/MII MAC auto mode */ #define LINK_MII_PHY 2 /* GMII/MII PHY auto mode */ #define LINKMODE_OFFSET 23 /* Link type offset */ #define P5_LINK_RGMII LINK_RGMII /* Port 5 RGMII mode */ #define P5_LINK_MII_MAC LINK_MII_MAC /* Port 5 GMII/MII MAC auto mode */ #define P5_LINK_MII_PHY LINK_MII_PHY /* Port 5 GMII/MII PHY auto mode */ #define P5_LINK_OFFSET LINKMODE_OFFSET /* Port 5 link type offset */ /*#define P4_USB_SEL (1 << 25) Select port USB interface */ #define EN_P5_LINK_PHY (1 << 26) /* Enable port 5 PHY provides link status to MAC */ #define EN_P4_LINK_PHY (1 << 25) /* Enable port 4 PHY provides link status to MAC */ #define EN_P3_LINK_PHY (1 << 24) /* Enable port 3 PHY provides link status to MAC */ #define EN_P2_LINK_PHY (1 << 23) /* Enable port 2 PHY provides link status to MAC */ #define EN_P1_LINK_PHY (1 << 22) /* Enable port 1 PHY provides link status to MAC */ #define EN_P0_LINK_PHY (1 << 21) /* Enable port 0 PHY provides link status to MAC */ /*When enabled, the authorized node are allowed in one direction ("IN" direction) to forward packet to the unauthorized node. Otherwise, it is not allowed. 0= BOTH direction. (control for the packets that "SA=" or "DA=" this MAC address.) 1= IN direction. (control for the packets that "SA=" this MAC address.) */ #define EN_8021X_TOGVLAN ( DOT1X_PROCESS_GVLAN<>Dot1xUNAUTHBH_OFFSET) /* Alias Name */ #define DOT1X_PROCESS_DROP (Dot1xUNAUTHBH_DROP>>Dot1xUNAUTHBH_OFFSET) /* Alias Name */ #define DOT1X_PROCESS_TOCPU (Dot1xUNAUTHBH_TOCPU>>Dot1xUNAUTHBH_OFFSET) /* Alias Name */ #define DOT1X_PROCESS_GVLAN (Dot1xUNAUTHBH_GVLAN>>Dot1xUNAUTHBH_OFFSET) /* Alias Name */ #define DOT1X_PROCESS_RESERVED (Dot1xUNAUTHBH_RESERVED>>Dot1xUNAUTHBH_OFFSET) /* Alias Name */ /* Link Aggregation Control Register (IEEE 802.3ad) */ #define LAGCR_BASE (SWCORE_BASE + 0x4C00) #define LAGHPMR0 (0x00 + LAGCR_BASE) /* Link Aggregation Hashed Index to Port Mapping Register 0 */ #define LAGCR0 (0x08 + LAGCR_BASE) /* Link Aggregation Control Register 0 */ #define LAGCR1 (0x0C + LAGCR_BASE) /* Link Aggregation Control Register 1 */ /* output queue stats mask */ #define OUTPUTQUEUE_STAT_MASK_CR0 0xfc000000 #define OUTPUTQUEUE_STAT_MASK_CR1 0x3fffffff /* LAGHPMR0 - Link Aggregation Hashed Index to Port Mapping Register 0 */ #define LAG_HASHIDX_BITNUM 4 /* LAGCR0 - Link Aggregation Control Register 0 */ #define TRUNKMASK_MASK (0x1ff) #define RTL865X_PORTMASK_UNASIGNED 0x5A5A5A5A #define RTL865X_PREALLOC_SKB_UNASIGNED 0xA5A5A5A5 #define RTL865XC_PORT_NUMBER 9 /* Spanning Tree Port State Definition */ #define RTL8651_PORTSTA_DISABLED 0x00 #define RTL8651_PORTSTA_BLOCKING 0x01 #define RTL8651_PORTSTA_LISTENING 0x02 #define RTL8651_PORTSTA_LEARNING 0x03 #define RTL8651_PORTSTA_FORWARDING 0x04 #define RTL8651_L2TBL_ROW 256 #define RTL8651_L2TBL_COLUMN 4 #define RTL865XC_LAGHASHIDX_NUMBER 8 /* There are 8 hash values in RTL865xC Link Aggregation. */ #define RTL865XC_VLAN_NUMBER 4096 //Ethernet port bandwidth control #define RTL8651_BC_FULL 0x00 #define RTL8651_BC_128K 0x01 #define RTL8651_BC_256K 0x02 #define RTL8651_BC_512K 0x03 #define RTL8651_BC_1M 0x04 #define RTL8651_BC_2M 0x05 #define RTL8651_BC_4M 0x06 #define RTL8651_BC_8M 0x07 #define RTL8651_BC_16M 0x08 #define RTL8651_BC_32M 0x09 #define RTL8651_BC_64M 0x0A /* For round robin ration */ #define RTL8651_RR_H_FIRST 0x03 #define RTL8651_RR_H16_L1 0x02 #define RTL8651_RR_H8_L1 0x01 #define RTL8651_RR_H4_L1 0x00 #define RTL865XC_NETINTERFACE_NUMBER 8 #define RTL8651_L2_NUMBER 1024 enum FDB_FLAGS { FDB_FWD = 0, FDB_SRCBLK = 1, FDB_TRAPCPU = 2, }; /* Miscellaneous control registers */ #define LEDCREG (SWCORE_BASE + 0x4300) /* LED control */ #define LEDCR1 (LEDCREG+0x04) #define LEDBCR (LEDCREG+0x0C) #define MISC_BASE (SWCORE_BASE + 0x00007000) //#define LEDCR (0x000 + MISC_BASE) /* LED control */ #define LEDCR (0x000 + SWCORE_BASE + 0x4300) /* LED control */ //????? #define BCR0 (0x008 + MISC_BASE) /* Input bandwidth control */ #define BCR1 (0x00C + MISC_BASE) /* Ouput bandwidth control */ #define FCREN (0x014 + MISC_BASE) /* Flow control enable control */ #define FCRTH (0x018 + MISC_BASE) /* Flow control threshold */ #define FCPTR (0x028 + MISC_BASE) /* Flow control prime threshold register */ #define PTCR (0x01C + MISC_BASE) /* Port trunk control */ #define SWTECR (0x020 + MISC_BASE) /* Switch table extended control */ #define PTRAPCR (0x024 + MISC_BASE) /* Protocol trapping control */ #define GIDXMCR (0x07C + MISC_BASE) /* GIDX mapping control */ #define PBVR2 (0x0A0 + MISC_BASE) /* Protocol-Based VLAN Rule 2 -- NetBIOS */ #define PBVR2E (0x0A4 + MISC_BASE) /* Protocol-Based VLAN Rule 2 Extended */ #define PBVR3 (0x0A8 + MISC_BASE) /* Protocol-Based VLAN Rule 3 -- PPPoE Control */ #define PBVR3E (0x0AC + MISC_BASE) /* Protocol-Based VLAN Rule 3 Extended */ #define PBVR4 (0x0B0 + MISC_BASE) /* Protocol-Based VLAN Rule 4 -- PPPoE Session */ #define PBVR4E (0x0B4 + MISC_BASE) /* Protocol-Based VLAN Rule 4 Extended */ #define PBVR5 (0x0B8 + MISC_BASE) /* Protocol-Based VLAN Rule 5 -- User-defined 1*/ #define PBVR5E (0x0BC + MISC_BASE) /* Protocol-Based VLAN Rule 5 Extended */ #define PBVR6 (0x0C0 + MISC_BASE) /* Protocol-Based VLAN Rule 6 -- User-defined 2*/ #define PBVR6E (0x0C4 + MISC_BASE) /* Protocol-Based VLAN Rule 6 Extended */ #define PSIR0 (0x0C8 + MISC_BASE) /* Port State Information Register 0 */ #define PSIR1 (0x0CC + MISC_BASE) /* Port State Information Register 1 */ #define CHIPID (0x100 + MISC_BASE) /* Chip version ID */ /* LED control register field definitions */ #define LED_P0_SPEED (1 << 0) /* LED port 0 collision */ #define LED_P0_ACT (1 << 1) /* LED port 0 active */ #define LED_P0_COL (1 << 2) /* LED port 0 speed 100M */ #define LED_P1_SPEED (1 << 3) /* LED port 1 collision */ #define LED_P1_ACT (1 << 4) /* LED port 1 active */ #define LED_P1_COL (1 << 5) /* LED port 1 speed 100M */ #define LED_P2_SPEED (1 << 6) /* LED port 2 collision */ #define LED_P2_ACT (1 << 7) /* LED port 2 active */ #define LED_P2_COL (1 << 8) /* LED port 2 speed 100M */ #define LED_P3_SPEED (1 << 9) /* LED port 3 collision */ #define LED_P3_ACT (1 << 10) /* LED port 3 active */ #define LED_P3_COL (1 << 11) /* LED port 3 speed 100M */ #define LED_P4_SPEED (1 << 12) /* LED port 4 collision */ #define LED_P4_ACT (1 << 13) /* LED port 4 active */ #define LED_P4_COL (1 << 14) /* LED port 4 speed 100M */ #define LED_P5_SPEED (1 << 15) /* LED port 5 collision */ #define LED_P5_ACT (1 << 16) /* LED port 5 active */ #define LED_P5_COL (1 << 17) /* LED port 5 speed 100M */ #define EN_LED_CPU_CTRL (1 << 18) /* Enable CPU control LED */ /* Bandwidth control register field definitions */ #define OUT_BC_P0_OFFSET 0 /* Output bandwidth control port 0 offset */ #define IN_BC_P0_OFFSET 4 /* Input bandwidth control port 0 offset */ #define OUT_BC_P1_OFFSET 8 /* Output bandwidth control port 1 offset */ #define IN_BC_P1_OFFSET 12 /* Input bandwidth control port 1 offset */ #define OUT_BC_P2_OFFSET 16 /* Output bandwidth control port 2 offset */ #define IN_BC_P2_OFFSET 20 /* Input bandwidth control port 2 offset */ #define OUT_BC_P3_OFFSET 24 /* Output bandwidth control port 3 offset */ #define IN_BC_P3_OFFSET 48 /* Input bandwidth control port 3 offset */ #define OUT_BC_P4_OFFSET 0 /* Output bandwidth control port 4 offset */ #define IN_BC_P4_OFFSET 4 /* Input bandwidth control port 4 offset */ #define OUT_BC_P5_OFFSET 8 /* Output bandwidth control port 5 offset */ #define IN_BC_P5_OFFSET 12 /* Input bandwidth control port 5 offset */ #define BW_FULL_RATE 0 #define BW_128K 1 #define BW_256K 2 #define BW_512K 3 #define BW_1M 4 #define BW_2M 5 #define BW_4M 6 #define BW_8M 7 /* Checksum control register field definitions */ #define ALLOW_L2_CHKSUM_ERR (1 << 0) /* Allow L2 checksum error */ #define ALLOW_L3_CHKSUM_ERR (1 << 1) /* Allow L3 checksum error */ #define ALLOW_L4_CHKSUM_ERR (1 << 2) /* Allow L4 checksum error */ #define EN_ETHER_L3_CHKSUM_REC (1 << 3) /* Enable L3 checksum recalculation*/ #define EN_ETHER_L4_CHKSUM_REC (1 << 4) /* Enable L4 checksum recalculation*/ /* Flow control enable register field defintions */ #define EN_INQ_FC_CPU (1 << 31) /* Enable Flow Control on CPU Port */ #define EN_INQ_FC_5 (1 << 30) /* Enable Flow Control on Port 5 */ #define EN_INQ_FC_4 (1 << 29) /* Enable Flow Control on Port 4 */ #define EN_INQ_FC_3 (1 << 28) /* Enable Flow Control on Port 3 */ #define EN_INQ_FC_2 (1 << 27) /* Enable Flow Control on Port 2 */ #define EN_INQ_FC_1 (1 << 26) /* Enable Flow Control on Port 1 */ #define EN_INQ_FC_0 (1 << 25) /* Enable Flow Control on Port 0 */ #define EN_OUTQ_FC_CPU (1 << 24) /* Enable Flow Control on CPU Port */ #define EN_OUTQ_FC_5 (1 << 23) /* Enable Flow Control on Port 5 */ #define EN_OUTQ_FC_4 (1 << 22) /* Enable Flow Control on Port 4 */ #define EN_OUTQ_FC_3 (1 << 21) /* Enable Flow Control on Port 3 */ #define EN_OUTQ_FC_2 (1 << 20) /* Enable Flow Control on Port 2 */ #define EN_OUTQ_FC_1 (1 << 19) /* Enable Flow Control on Port 1 */ #define EN_OUTQ_FC_0 (1 << 18) /* Enable Flow Control on Port 0 */ #define CPU_LAUNCH_FC_P5 (1 << 17) /* CPU launch flow control of Port 5 */ #define CPU_LAUNCH_FC_P4 (1 << 16) /* CPU launch flow control of Port 4 */ #define CPU_LAUNCH_FC_P3 (1 << 15) /* CPU launch flow control of Port 3 */ #define CPU_LAUNCH_FC_P2 (1 << 14) /* CPU launch flow control of Port 2 */ #define CPU_LAUNCH_FC_P1 (1 << 13) /* CPU launch flow control of Port 1 */ #define CPU_LAUNCH_FC_P0 (1 << 12) /* CPU launch flow control of Port 0 */ #define EN_MDC_MDIO_FC (1 << 10) /* Enable MDC/MDIO Flow Control */ #define DSC_TH_OFFSET 0 /* Descriptor Initial threshold */ /* Flow control threshold register field defintions */ #define IN_Q_PER_PORT_BUF_FC_THH_OFFSET 24 /* InQ per port buffer page flow control high threshold offset */ #define IN_Q_PER_PORT_BUF_FC_THL_OFFSET 16 /* InQ per port buffer page flow control low threshold offset */ #define OUT_Q_PER_PORT_BUF_FC_THH_OFFSET 8 /* OutQ per port buffer page flow control high threshold offset */ #define OUT_Q_PER_PORT_BUF_FC_THL_OFFSET 0 /* OutQ per port buffer page flow control low threshold offset */ /* Flow control prime threshold register field defintions */ #define IN_Q_PTH_OFFSET 16 /* InQ Prime flow control threshold */ #define OUT_Q_PTH_OFFSET 0 /* OutQ Prime flow control threshold */ /* Port trunking control register field definitions */ #define LMPR7_OFFSET 27 /* Physical port index for logical port 7 */ #define LMPR6_OFFSET 24 /* Physical port index for logical port 6 */ #define LMPR5_OFFSET 21 /* Physical port index for logical port 5 */ #define LMPR4_OFFSET 18 /* Physical port index for logical port 4 */ #define LMPR3_OFFSET 15 /* Physical port index for logical port 3 */ #define LMPR2_OFFSET 12 /* Physical port index for logical port 2 */ #define LMPR1_OFFSET 9 /* Physical port index for logical port 1 */ #define LMPR0_OFFSET 6 /* Physical port index for logical port 0 */ #define TRUNK1_PORT_MASK_OFFSET 0 /* Physical port mask of trunk 1 */ /* Port trunking control register field definitions */ #define EN_PPP_OP (1 << 31) /* Enable PPPoE auto insert and remove */ /* Protocol trapping control register field definitions */ #define EN_ARP_TRAP (1 << 24) /* Enable trapping ARP packets */ #define EN_RARP_TRAP (1 << 25) /* Enable trapping RARP packets */ #define EN_PPPOE_TRAP (1 << 26) /* Enable trapping PPPoE packets */ #define EN_IGMP_TRAP (1 << 27) /* Enable trapping IGMP packets */ #define EN_DHCP_TRAP1 (1 << 28) /* Enable trapping DHCP 67 packets */ #define EN_DHCP_TRAP2 (1 << 29) /* Enable trapping DHCP 68 packets */ #define EN_OSPF_TRAP (1 << 30) /* Enable trapping OSPF packets */ #define EN_RIP_TRAP (1 << 31) /* Enable trapping RIP packets */ /* Spanning tree control register field definitions */ #define EN_ESTP_S_DROP (1 << 5) /* Enable egress spanning tree forward S_Drop */ /* Broadcast storm control register field definitions */ #define EN_BCAST_STORM (1 << 0) /* Enable broadcast storm control */ #define BCAST_TH_MASK (0xFF << 1) /* Threshold within broadcast interval mask */ #define BCAST_TH_OFFSET 1 /* Threshold within broadcast interval offset */ #define TI_100M_MASK (0x3F << 9) /* Time interval for 100M mask */ #define TI_100M_OFFSET 9 /* Time interval for 100M offset */ #define TI_10M_MASK (0x3F << 15)/* Time interval for 10M mask */ #define TI_10M_OFFSET 15 /* Time interval for 10M offset */ #define EN_L2LRUHASH (1<<4) /*Enable L2 Table hash collision over write the last used entry mode*/ #define EN_L2FASTAGING (1<<5) /*Enable L2 Fast Aging Out*/ /* Table entry aging time control register field definitions */ #define ICMP_TH_OFFSET 26 /* ICMP timeout threshold offset */ #define ICMP_TH_MASK (0x3f << ICMP_TH_OFFSET) #define UDP_TH_OFFSET 20 /* UDP timeout threshold offset */ #define UDP_TH_MASK (0x3f << UDP_TH_OFFSET) #define TCP_LONG_TH_OFFSET 14 /* TCP long timeout threshold offset */ #define TCP_LONG_TH_MASK (0x3f << TCP_LONG_TH_OFFSET) #define TCP_MED_TH_OFFSET 8 /* TCP medium timeout threshold offset */ #define TCP_MED_TH_MASK (0x3f << TCP_MED_TH_OFFSET) #define TCP_FAST_TH_OFFSET 2 /* TCP fast timeout threshold offset */ #define TCP_FAST_TH_MASK (0x3f << TCP_FAST_TH_OFFSET) /* Port mirror control register field definitions */ #define MIRROR_TO_PORT_OFFSET 26 /* Port receiving the mirrored traffic offset */ #define MIRROR_FROM_PORT_RX_OFFSET 20 /* Rx port to be mirrored offset */ #define MIRROR_FROM_PORT_TX_OFFSET 14 /* Tx port to be mirrored offset */ /* Per port matching action register field definitions */ #define EN_PMATCH_PORT_LIST_OFFSET 26 /* Enable pattern match port list offset */ #define MATCH_OP_P5_OFFSET 24 /* Offset of operation if matched on port 5 */ #define MATCH_OP_P4_OFFSET 22 /* Offset of operation if matched on port 4 */ #define MATCH_OP_P3_OFFSET 20 /* Offset of operation if matched on port 3 */ #define MATCH_OP_P2_OFFSET 18 /* Offset of operation if matched on port 2 */ #define MATCH_OP_P1_OFFSET 16 /* Offset of operation if matched on port 1 */ #define MATCH_OP_P0_OFFSET 14 /* Offset of operation if matched on port 0 */ #define MATCH_DROP 0 /* Drop if matched */ #define MATCH_MIRROR_TO_CPU 1 /* Mirror to CPU if matched */ #define MATCH_FORWARD_TO_CPU 2 /* Forward to CPU if matched */ #define MATCH_TO_MIRROR_PORT 3 /* To mirror port if matched */ /* Port based vlan config register field definitions */ #define PVID_MASK 7 /* MASK for PVID */ #define VIDP0_OFFSET 0 /* Vlan table index for port 0 */ #define VIDP1_OFFSET 3 /* Vlan table index for port 1 */ #define VIDP2_OFFSET 6 /* Vlan table index for port 2 */ #define VIDP3_OFFSET 9 /* Vlan table index for port 3 */ #define VIDP4_OFFSET 12 /* Vlan table index for port 4 */ #define VIDP5_OFFSET 15 /* Vlan table index for port 5 */ /* GIDX mapping control register field definitions */ #define GIDX_MASK 7 /* MASK for GIDX */ #define GIDX0_OFFSET 0 /* Index to IP table */ #define GIDX1_OFFSET 3 /* Index to IP table */ #define GIDX2_OFFSET 6 /* Index to IP table */ #define GIDX3_OFFSET 9 /* Index to IP table */ #define GIDX4_OFFSET 12 /* Index to IP table */ #define GIDX5_OFFSET 15 /* Index to IP table */ #define GIDX6_OFFSET 18 /* Index to IP table */ #define GIDX7_OFFSET 21 /* Index to IP table */ /* Offset control register field definitions */ #define OCR_START_MASK (0x1f << 26) /* Starting value of offset mask */ #define OCR_START_OFFSET 26 /* Starting value of offset offset */ #define OCR_END_MASK (0x1f << 20) /* End value of offset mask */ #define OCR_END_OFFSET 20 /* End value of offset offset */ /* Protocol-based VLAN Control Register field definitions */ #define PBVCR_PROTO_TYPE_OFFSET 0 /* Protocol-Based VLAN Control Register Protocol Type */ #define PBVCR_PROTO_TYPE_MASK (0x3 << PBVCR_PROTO_TYPE_OFFSET) #define PBVCR_PROTO_VALUE_OFFSET 2 /* Protocol-Based VLAN Control Register Protocol Value */ #define PBVCR_PROTO_VALUE_MASK (0xffff << PBVCR_PROTO_VALUE_OFFSET) #define PBVCR_VIDXP5_OFFSET 21 /* VLAN index for Port 5 */ #define PBVCR_VIDXP5_MASK (0x7 << PBVCR_VIDXP5_OFFSET) #define PBVCR_VP5_OFFSET 20 /* Valid bit for Port 5 */ #define PBVCR_VP5_MASK (0x1 << PBVCR_VP5_OFFSET) #define PBVCR_VIDXP4_OFFSET 17 /* VLAN index for Port 4 */ #define PBVCR_VIDXP4_MASK (0x7 << PBVCR_VIDXP4_OFFSET) #define PBVCR_VP4_OFFSET 16 /* Valid bit for Port 4 */ #define PBVCR_VP4_MASK (0x1 << PBVCR_VP4_OFFSET) #define PBVCR_VIDXP3_OFFSET 13 /* VLAN index for Port 3 */ #define PBVCR_VIDXP3_MASK (0x7 << PBVCR_VIDXP3_OFFSET) #define PBVCR_VP3_OFFSET 12 /* Valid bit for Port 3 */ #define PBVCR_VP3_MASK (0x1 << PBVCR_VP3_OFFSET) #define PBVCR_VIDXP2_OFFSET 9 /* VLAN index for Port 2 */ #define PBVCR_VIDXP2_MASK (0x7 << PBVCR_VIDXP2_OFFSET) #define PBVCR_VP2_OFFSET 8 /* Valid bit for Port 2 */ #define PBVCR_VP2_MASK (0x1 << PBVCR_VP2_OFFSET) #define PBVCR_VIDXP1_OFFSET 5 /* VLAN index for Port 1 */ #define PBVCR_VIDXP1_MASK (0x7 << PBVCR_VIDXP1_OFFSET) #define PBVCR_VP1_OFFSET 4 /* Valid bit for Port 1 */ #define PBVCR_VP1_MASK (0x1 << PBVCR_VP1_OFFSET) #define PBVCR_VIDXP0_OFFSET 3 /* VLAN index for Port 0 */ #define PBVCR_VIDXP0_MASK (0x7 << PBVCR_VIDXP0_OFFSET) #define PBVCR_VP0_OFFSET 0 /* Valid bit for Port 0 */ #define PBVCR_VP0_MASK (0x1 << PBVCR_VP0_OFFSET) #define PBVCR_VIDXEP2_OFFSET 9 /* VLAN index for Extented Port 2 */ #define PBVCR_VIDXEP2_MASK (0x7 << PBVCR_VIDXEP2_OFFSET) #define PBVCR_VEP2_OFFSET 8 /* Valid bit for Extented Port 2 */ #define PBVCR_VEP2_MASK (0x1 << PBVCR_VEP2_OFFSET) #define PBVCR_VIDXEP1_OFFSET 5 /* VLAN index for Extented Port 1 */ #define PBVCR_VIDXEP1_MASK (0x7 << PBVCR_VIDXEP1_OFFSET) #define PBVCR_VEP1_OFFSET 4 /* Valid bit for Extented Port 1 */ #define PBVCR_VEP1_MASK (0x1 << PBVCR_VEP1_OFFSET) #define PBVCR_VIDXEP0_OFFSET 1 /* VLAN index for Extented Port 0 */ #define PBVCR_VIDXEP0_MASK (0x7 << PBVCR_VIDXEP0_OFFSET) #define PBVCR_VEP0_OFFSET 0 /* Valid bit for Extented Port 0 */ #define PBVCR_VEP0_MASK (0x1 << PBVCR_VEP0_OFFSET) #if 0 /* Not defined in 865xC spec */ /* PCMCIA registers */ #define PCMCIA_BASE (SYSTEM_BASE+0x0000) /* 0xBD010000 */ #define PCMCIA_CFR (0x000 + PCMCIA_BASE) /* PCMCIA Command FIFO Register */ #define PCMCIA_IER (0x004 + PCMCIA_BASE) /* PCMCIA Interrupt enable register */ #define PCMCIA_FCR (0x008 + PCMCIA_BASE) /* PCMCIA FIFO control register */ #define PCMCIA_ISR (0x00C + PCMCIA_BASE) /* PCMCIA Interrupt Status register */ #define PCTCR (0x010 + PCMCIA_BASE) /* PCMCIA Timing Control Register */ //PCMCIA CFG #define RD_PCMCIA_ATTR 0x10000000 #define WR_PCMCIA_ATTR 0x00000000 #define RD_PCMCIA_IO 0x14000000 #define WR_PCMCIA_IO 0x04000000 //PCMCIA IER #define ERDAI 0x80000000 #define ERFEI (1<<30) #define ERFFI (1<<29) #define ECFDI (1<<28) #define ECFEI (1<<27) #define ECFFI (1<<26) //PCMCIA FCR #define EFIFO 0x80000000 #define RFRST (1<<30) #define TFRST (1<<29) #define RTRG_MASK (0x3<<27) #define RTRG_01 (0x0<<27) #define RTRG_12 (0x1<<27) #define RTRG_16 (0x2<<27) #define RTRG_26 (0x3<<27) #define RFRC_MASK (0x3f<<21) #define CFRC_MASK (0x3f<<15) //PCMCIA LSR #define DR 0x80000000 #define RxEMPTY (1<<30) #define RxqFULL (1<<29) #define CMOK (1<<28) #define CMEMPTY (1<<27) #define CMFULL (1<<26) #endif /* UART registers */ #define UART0_BASE (SYSTEM_BASE+0x2000) /* 0xB8002000 */ #define UART1_BASE (SYSTEM_BASE+0x2100) /* System Control Registers */ /* Global interrupt control registers */ #define GICR_BASE (SYSTEM_BASE+0x3000) /* 0xB8003000 */ #define GIMR (0x000 + GICR_BASE) /* Global interrupt mask */ #define GISR (0x004 + GICR_BASE) /* Global interrupt status */ #define IRR (0x008 + GICR_BASE) /* Interrupt routing */ #define IRR0 (0x008 + GICR_BASE) /* Interrupt routing */ #define IRR1 (0x00C + GICR_BASE) /* Interrupt routing */ #define IRR2 (0x010 + GICR_BASE) /* Interrupt routing */ #define IRR3 (0x014 + GICR_BASE) /* Interrupt routing */ /* Global interrupt mask register field definitions */ #define TCIE (1 << 29) /* Timer/Counter interrupt enable */ #define USBIE (1 << 30) /* USB interrupt enable */ #define PCMCIAIE (1 << 29) /* PCMCIA interrupt enable */ #define UART1IE (1 << 28) /* UART 1 interrupt enable */ #define UART0IE (1 << 27) /* UART 0 interrupt enable */ #define PCIIE (1 << 26) /* Parallel port interrupt enable */ #define SWIE (1 << 25) /* Switch core interrupt enable */ #define PABCIE (1 << 24) /* GPIO port ABC interrupt enable */ #define IREQ0IE (1 << 23) /* External interrupt 0 enable */ #define LBCTMOIE (1 << 21) /* LBC time-out interrupt enable */ #ifdef CONFIG_RTL865XB #define CRYPTOIE (1 << 20) /* Crypto engine interrupt enable */ #define AUTHIE (1 << 19) /* Authentication engine interupt enable */ #define PCMIE (1 << 18) /* PCM interface interrupt enable */ #define PDEIE (1 << 17) /* GPIO port D,E,F,G,H,I interrupt enable */ #define PCIBTMOIE (1 << 16) /* PCI bridge time-out interrupt enable */ #endif /*CONFIG_RTL865XB*/ /* Global interrupt status register field definitions */ #define TCIP (1 << 31) /* Timer/Counter interrupt pending */ #define USBIP (1 << 30) /* USB host interrupt pending */ #define PCMCIAIP (1 << 29) /* PCMCIA interrupt pending */ #define UART1IP (1 << 28) /* UART 1 interrupt pending */ #define UART0IP (1 << 27) /* UART 0 interrupt pending */ #define PCIIP (1 << 26) /* PCI host interrupt pending */ #define SWIP (1 << 25) /* Switch core interrupt pending */ #define PABCIP (1 << 24) /* GPIO port ABC interrupt pending */ #define IREQIP (1 << 23) /* External interrupt 0 pending */ #define LBCTMOIP (1 << 21) /* LBC time-out interrupt pending */ #ifdef CONFIG_RTL865XB #define CRYPTOIP (1 << 20) /* Crypto engine interrupt pending */ #define AUTHIP (1 << 19) /* Authentication engine interupt pending */ #define PCMIP (1 << 18) /* PCM interface interrupt pending */ #define PDEIP (1 << 17) /* GPIO port D,E,F,G,H,I interrupt pending */ #define PCIBTMOIP (1 << 16) /* PCI bridge time-out interrupt pending */ #endif /*CONFIG_RTL865XB*/ #define LX0_BFRAME_IP (1 << 1) /* LBC 0 bus frame time-out interrupt pending flag */ /* Interrupt routing register field definitions */ #define TCIRS_OFFSET 30 /* Timer/Counter interrupt routing select offset */ #define USBIRS_OFFSET 28 /* USB interrupt routing select offset */ #define PCMCIAIRS_OFFSET 26 /* PCI interrupt routing select offset */ #define UART1IRS_OFFSET 24 /* UART 1 interrupt routing select offset */ #define UART0IRS_OFFSET 22 /* UART 0 interrupt routing select offset */ #define PCIIRS_OFFSET 20 /* USB 1 interrupt routing select offset */ #define SWIRS_OFFSET 18 /* Switch core interrupt routing select offset */ #define PABCIRS_OFFSET 16 /* GPIO port B interrupt routing select offset */ #define IREQ0RS_OFFSET 14 /* External interrupt 0 routing select offset */ #define LBCTMOIRS_OFFSET 10 /* LBC time-out interrupt routing select offset */ #ifdef CONFIG_RTL865XB #define TCIRS_MSB_OFFSET 9 /* Timer/Counter interrupt routing select MSB offset */ #define USBIRS_MSB_OFFSET 8 /* USB interrupt routing select MSB offset */ #define PCMCIAIRS_MSB_OFFSET 7 /* PCI interrupt routing select MSB offset */ #define UART1IRS_MSB_OFFSET 6 /* UART 1 interrupt routing select MSB offset */ #define UART0IRS_MSB_OFFSET 5 /* UART 0 interrupt routing select MSB offset */ #define PCIIRS_MSB_OFFSET 4 /* USB 1 interrupt routing select MSB offset */ #define SWIRS_MSB_OFFSET 3 /* Switch core interrupt routing select MSB offset */ #define PABCIRS_MSB_OFFSET 2 /* GPIO port B interrupt routing select MSB offset */ #define IREQ0RS_MSB_OFFSET 1 /* External interrupt 0 routing select MSB offset */ #define LBCTMOIRS_MSB_OFFSET 0 /* LBC time-out interrupt routing select MSB offset */ #define CRYPTIRS_OFFSET 29 /* Crypto engine interrupt routing select offset */ #define AUTHIRS_OFFSET 26 /* Authentication engine interrupt routing select offset */ #define PCMIRS_OFFSET 23 /* PCM interface interrupt routing select offset */ #define PDEIRS_OFFSET 20 /* GPIO port D,E,F,G,H,I interrupt routing select MSB offset */ #define PCIBTMOIRS_OFFSET 17 /* PCI bridge time-out interrupt routing select MSB offset */ #endif /*CONFIG_RTL865XB*/ /* Timer control registers */ #define TIMER_BASE (SYSTEM_BASE+0x3100) /* 0xB8003100 */ #define TC0DATA (0x000 + TIMER_BASE) /* Timer/Counter 0 data */ #define TC1DATA (0x004 + TIMER_BASE) /* Timer/Counter 1 data */ #define TC0CNT (0x008 + TIMER_BASE) /* Timer/Counter 0 count */ #define TC1CNT (0x00C + TIMER_BASE) /* Timer/Counter 1 count */ #define TCCNR (0x010 + TIMER_BASE) /* Timer/Counter control */ #define TCIR (0x014 + TIMER_BASE) /* Timer/Counter intertupt */ #define CDBR (0x018 + TIMER_BASE) /* Clock division base */ #define WDTCNR (0x01C + TIMER_BASE) /* Watchdog timer control */ /* Timer/Counter data register field definitions */ #define TCD_OFFSET 8 /* Timer/Counter control register field defintions */ #define TC0EN (1 << 31) /* Timer/Counter 0 enable */ #define TC0MODE_COUNTER 0 /* Timer/Counter 0 counter mode */ #define TC0MODE_TIMER (1 << 30) /* Timer/Counter 0 timer mode */ #define TC1EN (1 << 29) /* Timer/Counter 1 enable */ #define TC1MODE_COUNTER 0 /* Timer/Counter 1 counter mode */ #define TC1MODE_TIMER (1 << 28) /* Timer/Counter 1 timer mode */ /* Timer/Counter interrupt register field definitions */ #define TC0IE ((uint32)1 << 31) /* Timer/Counter 0 interrupt enable */ #define TC1IE (1 << 30) /* Timer/Counter 1 interrupt enable */ #define TC0IP (1 << 29) /* Timer/Counter 0 interrupt pending */ #define TC1IP (1 << 28) /* Timer/Counter 1 interrupt pending */ /* Clock division base register field definitions */ #define DIVF_OFFSET 16 /* Watchdog control register field definitions */ #define WDTE_OFFSET 24 /* Watchdog enable */ #define WDSTOP_PATTERN 0xA5 /* Watchdog stop pattern */ #define WDTCLR (1 << 23) /* Watchdog timer clear */ #define OVSEL_15 0 /* Overflow select count 2^15 */ #define OVSEL_16 (1 << 21) /* Overflow select count 2^16 */ #define OVSEL_17 (2 << 21) /* Overflow select count 2^17 */ #define OVSEL_18 (3 << 21) /* Overflow select count 2^18 */ #define WDTIND (1 << 20) /* Indicate whether watchdog ever occurs */ /* RTC control register field definitions */ #define WRITE_CDLW_OK (1 << 31) /* Write CDLW OK */ #define RTCSEL (1 << 30) /* Fase mode */ #define RTCEN (1 << 29) /* Enable */ /* System clock generation */ #define SCCR (SYSTEM_BASE+0x3200) /* 0xB8003200 System Clock Control Register */ #define DPLCR0 (SCCR+0x04) /* DPLL Clock Control Register 0 */ #define DPLCR1 (SCCR+0x08) /* DPLL Clock Control Register 1 */ #define PCCR (SCCR+0x0C) /* Peripheral Clock Control Register */ #define SCCR_CPU_OFFSET 4 /* SCCR CPU(Lexra Bus 0) status offset */ #define SCCR_STATUS_MASK 0x07 /* SCCR LexaBus0/LexaBus1/Memory mask */ #define EN_S0DPLL (1 << 31) /* Enable S0DPLL Tuning */ #define EN_S1DPLL (1 << 30) /* Enable S1DPLL Tuning */ #define EN_MDPLL (1 << 31) /* Enable MDPLL Tuning */ #define S0UPDPLL_MASK 0x3F /* S0_UP_DPLL mask*/ #define MUPDPLL_MASK 0x3F /* M_UP_DPLL mask*/ #define S0DOWNDPLL_MASK 0x1F /* S0_DOWN_DPLL mask*/ #define MDOWNDPLL_MASK 0x1F /* M_DOWN_DPLL mask*/ #define S0UPDPLL_OFFSET 16 /* S0_UP_DPLL status offset*/ #define MUPDPLL_OFFSET 5 /* M_UP_DPLL status offset*/ #define S0DOWNDPLL_OFFSET 11 /* S0_DOWN_DPLL status offset*/ #define MDOWNDPLL_OFFSET 0 /* M_DOWN_DPLL status offset*/ #define S0DOWNDPLL_VALUE (9 << S0DOWNDPLL_OFFSET) /* S0_DOWN_DPLL default test value*/ #define S0UPDPLL_VALUE_225MHZ (17 << S0UPDPLL_OFFSET) /* S0_UP_DPLL test value 0*/ #define S0UPDPLL_VALUE_250MHZ (19 << S0UPDPLL_OFFSET) /* S0_UP_DPLL test value 1*/ #define S0UPDPLL_VALUE_275MHZ (21 << S0UPDPLL_OFFSET) /* S0_UP_DPLL test value 2*/ #define S0UPDPLL_VALUE_300MHZ (23 << S0UPDPLL_OFFSET) /* S0_UP_DPLL test value 3*/ #define S0UPDPLL_VALUE_325MHZ (25 << S0UPDPLL_OFFSET) /* S0_UP_DPLL test value 4*/ #define S0UPDPLL_VALUE_350MHZ (27 << S0UPDPLL_OFFSET) /* S0_UP_DPLL test value 5*/ #define S0UPDPLL_VALUE_375MHZ (29 << S0UPDPLL_OFFSET) /* S0_UP_DPLL test value 6*/ #define S0UPDPLL_VALUE_400MHZ (31 << S0UPDPLL_OFFSET) /* S0_UP_DPLL test value 7*/ #define S0UPDPLL_VALUE_NUM 8 /* S0_UP_DPLL total test values */ #define S0UPDPLL_VALUE_DEFAULT S0UPDPLL_VALUE_275MHZ /* S0_UP_DPLL default test value */ #define MDOWNDPLL_VALUE (9 << MDOWNDPLL_OFFSET) /* M_DOWN_DPLL default test value*/ #define MUPDPLL_VALUE_137MHZ (10 << MUPDPLL_OFFSET) /* M_UP_DPLL test value 0*/ #define MUPDPLL_VALUE_150MHZ (11 << MUPDPLL_OFFSET) /* M_UP_DPLL test value 1*/ #define MUPDPLL_VALUE_162MHZ (12 << MUPDPLL_OFFSET) /* M_UP_DPLL test value 2*/ #define MUPDPLL_VALUE_175MHZ (13 << MUPDPLL_OFFSET) /* M_UP_DPLL test value 3*/ #define MUPDPLL_VALUE_187MHZ (14 << MUPDPLL_OFFSET) /* M_UP_DPLL test value 4*/ #define MUPDPLL_VALUE_NUM 5 /* M_UP_DPLL total test values */ #define MUPDPLL_VALUE_DEFAULT MUPDPLL_VALUE_137MHZ /* M_UP_DPLL default test value */ #if defined(CONFIG_RTL_819X) /*Shared Pin Register Set */ #ifdef CONFIG_RTL_8196B #define PIN_MUX_SEL (SYSTEM_BASE+0x30) /* 0xB8000030 - 0xB8000033 */ #else #define PIN_MUX_SEL 0xb8000040 #endif /* Shared Pin Register field definitions */ #define REG_IOCFG_POMII (3 << 0) /* P0-MII Shared Pin Control Bits */ #define REG_IOCFG_PCIE (3 << 2) /* PCIE Shared Pin Control Bits */ #define REG_IOCFG_UART (3 << 5) /* UART Shared Pin Control Bits */ #define REG_IOCFG_JTAG (7 << 7) /* JTAG Shared Pin Control Bits */ #define REG_IOCFG_LED_S0 (3 << 10) /* LEDSIG0 Shared Pin Control Bits */ #define REG_IOCFG_LED_S1 (3 << 12) /* LEDSIG1 Shared Pin Control Bits */ #define REG_IOCFG_LED_S2 (3 << 14) /* LEDSIG2 Shared Pin Control Bits */ #define REG_IOCFG_LED_S3 (3 << 16) /* LEDSIG3 Shared Pin Control Bits */ #define REG_IOCFG_LED_P0 (3 << 18) /* LEDPHASE0 Shared Pin Control Bits */ #define REG_IOCFG_LED_P1 (3 << 20) /* LEDPHASE1 Shared Pin Control Bits */ #define REG_IOCFG_LED_P2 (3 << 22) /* LEDPHASE2 Shared Pin Control Bits */ #define REG_IOCFG_LED_P3 (3 << 24) /* LEDPHASE3 Shared Pin Control Bits */ #define REG_IOCFG_LED_P4 (3 << 26) /* LEDPHASE4 Shared Pin Control Bits */ #endif /* GPIO Register Set */ #define GPIO_BASE (SYSTEM_BASE+0x3500) /* 0xB8003500 */ #define PABCD_CNR (GPIO_BASE + 0x00) #define PABCD_PTYPE (GPIO_BASE + 0x04) #define PABCD_DIR (GPIO_BASE + 0x08) #define PABCD_DAT (GPIO_BASE + 0x0C) #define PABCD_ISR (GPIO_BASE + 0x10) #define PAB_IMR (GPIO_BASE + 0x14) #define PCD_IMR (GPIO_BASE + 0x18) #define PEFGH_CNR (GPIO_BASE + 0x1C) #define PEFGH_PTYPE (GPIO_BASE + 0x20) #define PEFGH_DIR (GPIO_BASE + 0x24) #define PEFGH_DAT (GPIO_BASE + 0x28) #define PEFGH_ISR (GPIO_BASE + 0x2C) #define PEF_IMR (GPIO_BASE + 0x30) #define PGH_IMR (GPIO_BASE + 0x34) #define PABCDCNR_REG (0x000 + GPIO_BASE) /* Port ABCD control */ #define PABCDPTYPE_REG (0x004 + GPIO_BASE) /* Port ABCD type */ #define PABCDDIR_REG (0x008 + GPIO_BASE) /* Port ABCD direction */ #define PABCDDAT_REG (0x00C + GPIO_BASE) /* Port ABCD data */ #define PABCDISR_REG (0x010 + GPIO_BASE) /* Port ABCD interrupt status */ #define PABIMR_REG (0x014 + GPIO_BASE) /* Port AB interrupt mask */ #define PCDIMR_REG (0x018 + GPIO_BASE) /* Port CD interrupt mask */ #define PEFGHCNR_REG (0x01C + GPIO_BASE) /* Port ABCD control */ #define PEFGHPTYPE_REG (0x020 + GPIO_BASE) /* Port ABCD type */ #define PEFGHDIR_REG (0x024 + GPIO_BASE) /* Port ABCD direction */ #define PEFGHDAT_REG (0x028 + GPIO_BASE) /* Port ABCD data */ #define PEFGHISR_REG (0x02C + GPIO_BASE) /* Port ABCD interrupt status */ #define PEFIMR_REG (0x030 + GPIO_BASE) /* Port AB interrupt mask */ #define PGHIMR_REG (0x034 + GPIO_BASE) /* Port CD interrupt mask */ /*added by Mark*/ /*PCI control regs*/ #define PCI_CTRL_BASE (SYSTEM_BASE+0x3400) /* 0xB8003400 */ /* GPIO control registers */ #define GPIO_BASE (SYSTEM_BASE+0x3500) /* 0xB8003500 */ #define PABCNR (0x00C + GPIO_BASE) /* Port AB control */ #define PABDIR (0x010 + GPIO_BASE) /* Port AB direction */ #define PABDAT (0x014 + GPIO_BASE) /* Port AB data */ #define PABISR (0x018 + GPIO_BASE) /* Port AB interrupt status */ /* #define PABIMR (0x01C + GPIO_BASE) */ /* Port AB interrupt mask */ /* #define PCIMR (0x050 + GPIO_BASE) */ /* Port C interrupt mask */ /* Port ABC data register field definitions */ #define PDA_OFFSET 24 /* Port A data offset */ #define PDB_OFFSET 16 /* Port B data offset */ #define PDC_OFFSET 8 /* Port C data offset */ /* Port ABC interrupt status register field definitions */ #define PAIP_OFFSET 24 /* Port A pending status offset */ #define PBIP_OFFSET 16 /* Port B pending status offset */ #define PCIP_OFFSET 8 /* Port C pending status offset */ /* Peripheral Lexra timing control registers */ #define PLTC (0x064 + GICR_BASE) /* Peripheral Lexra timeout control */ /* Peripheral Lexra timeout control register field definitions */ #define TOEN (1 << 31) #define TOLIMIT_2_7 (0 << 28) #define TOLIMIT_2_8 (1 << 28) #define TOLIMIT_2_9 (2 << 28) #define TOLIMIT_2_10 (3 << 28) #define TOLIMIT_2_11 (4 << 28) #define TOLIMIT_2_12 (5 << 28) #define TOLIMIT_2_13 (6 << 28) #define TOLIMIT_2_14 (7 << 28) /* Memory Control Register registers */ #define MCR_BASE (SYSTEM_BASE+0x1000) /* 0xB8001000 */ #define MCR (0x000 + MCR_BASE) /* Memory configuration register */ #define MTCR0 (0x004 + MCR_BASE) /* Memory timing configuration register */ #define MTCR1 (0x008 + MCR_BASE) /* Memory timing configuration register */ #define PFCR (0x010 + MCR_BASE) /* Pre-Fetch Control Register */ #define MPMR (0x040 + MCR_BASE) #if defined(CONFIG_RTL_819X) #define SDRDRAM_MASK (0x1<<31) #define DCR (0x004 + MCR_BASE) /* DRAM control register */ #define COLCNT_MASK (0x1c00000) #define COLCNT_OFFSET 22 #define ROWCNT_MASK (0x6000000) #define ROWCNT_OFFSET 25 #endif // MPMR 0xB8001040 Memory Power Management Register #define PM_MODE_OFFSET 30 #define PM_MODE_NORMAL (0 << PM_MODE_OFFSET) #define PM_MODE_ENABLE_AUTOMATIC_POWER_DOWN (1 << PM_MODE_OFFSET) #define PM_MODE_ENABLE_SELF_REFRESH (2 << PM_MODE_OFFSET) #define CRYPTO_BASE (SYSTEM_BASE+0xC000) /* 0xB801C000 */ #define IPSSDAR (CRYPTO_BASE+0x00) /* IPSec Source Descriptor Starting Address Register */ #define IPSDDAR (CRYPTO_BASE+0x04) /* IPSec Destination Descriptor Starting Address Register */ #define IPSCSR (CRYPTO_BASE+0x08) /* IPSec Command/Status Register */ #define IPSCTR (CRYPTO_BASE+0x0C) /* IPSec Control Register */ /* IPSec Command/Status Register */ #define IPS_SDUEIP (1<<15) /* Source Descriptor Unavailable Error Interrupt Pending */ #define IPS_SDLEIP (1<<14) /* Source Descriptor Length Error Interrupt Pending */ #define IPS_DDUEIP (1<<13) /* Destination Descriptor Unavailable Error Interrupt Pending */ #define IPS_DDOKIP (1<<12) /* Destination Descriptor OK Interrupt Pending */ #define IPS_DABFIP (1<<11) /* Data Address Buffer Interrupt Pending */ #define IPS_POLL (1<<1) /* Descriptor Polling. Set 1 to kick crypto engine to fetch source descriptor. */ #define IPS_SRST (1<<0) /* Software reset, write 1 to reset */ /* IPSec Control Register */ #define IPS_SDUEIE (1<<15) /* Source Descriptor Unavailable Error Interrupt Enable */ #define IPS_SDLEIE (1<<14) /* Source Descriptor Length Error Interrupt Enable */ #define IPS_DDUEIE (1<<13) /* Destination Descriptor Unavailable Error Interrupt Enable */ #define IPS_DDOKIE (1<<12) /* Destination Descriptor OK Interrupt Enable */ #define IPS_DABFIE (1<<11) /* Data Address Buffer Interrupt Enable */ #define IPS_LBKM (1<<8) /* Loopback mode enable */ #define IPS_SAWB (1<<7) /* Source Address Write Back */ #define IPS_CKE (1<<6) /* Clock enable */ #define IPS_DMBS_MASK (0x7<<3) /* Mask for Destination DMA Maximum Burst Size */ #define IPS_DMBS_16 (0x0<<3) /* 16 Bytes */ #define IPS_DMBS_32 (0x1<<3) /* 32 Bytes */ #define IPS_DMBS_64 (0x2<<3) /* 64 Bytes */ #define IPS_DMBS_128 (0x3<<3) /* 128 Bytes */ #define IPS_SMBS_MASK (0x7<<0) /* Mask for SourceDMA Maximum Burst Size */ #define IPS_SMBS_16 (0x0<<0) /* 16 Bytes */ #define IPS_SMBS_32 (0x1<<0) /* 32 Bytes */ #define IPS_SMBS_64 (0x2<<0) /* 64 Bytes */ #define IPS_SMBS_128 (0x3<<0) /* 128 Bytes */ /* PCM */ #define PCM_BASE (SYSTEM_BASE+0x8000) /* 0xB8008000 */ #define PCM_GCR (PCM_BASE+0x00) /* PCM Generic Control Register */ #define PCM_SCR (PCM_BASE+0x04) /* PCM Specific Control Register */ #define PCM_TSAR (PCM_BASE+0x08) /* PCM Time Slot Assignment Register */ #define PCM_BSIZE (PCM_BASE+0x0C) /* PCM Buffer Size Register */ #define PCM_CH0TXBSA (PCM_BASE+0x10) /* PCM Channel 0 Tx Buffer Starting Address */ #define PCM_CH1TXBSA (PCM_BASE+0x14) /* PCM Channel 1 Tx Buffer Starting Address */ #define PCM_CH2TXBSA (PCM_BASE+0x18) /* PCM Channel 2 Tx Buffer Starting Address */ #define PCM_CH3TXBSA (PCM_BASE+0x1C) /* PCM Channel 3 Tx Buffer Starting Address */ #define PCM_CH0RXBSA (PCM_BASE+0x20) /* PCM Channel 0 Rx Buffer Starting Address */ #define PCM_CH1RXBSA (PCM_BASE+0x24) /* PCM Channel 1 Rx Buffer Starting Address */ #define PCM_CH2RXBSA (PCM_BASE+0x28) /* PCM Channel 2 Rx Buffer Starting Address */ #define PCM_CH3RXBSA (PCM_BASE+0x2C) /* PCM Channel 3 Rx Buffer Starting Address */ #define PCM_IMR (PCM_BASE+0x30) /* PCM Interrupt Mask Register */ #define PCM_ISR (PCM_BASE+0x34) /* PCM Interrupt Status Register */ #define PAGE1_PCM_OWN ( 1 << 1 ) #define PAGE0_PCM_OWN ( 1 << 0 ) #define PCM_PAGE0 0 #define PCM_PAGE1 1 #define PCM_CHANNEL0 0 #define PCM_CHANNEL1 1 #define PCM_CHANNEL2 2 #define PCM_CHANNEL3 3 #define PCM_LINEAR 0 #define PCM_ALAW 1 #define PCM_ULAW 2 /* PCM Generic Control Register */ #define PCM_AE (1<<12) /* Interrupt Enable */ #define PCM_CLKDIR (1<<11) /* 0:external source from codec, 1:internal PLL */ #define PCM_EXDSE (1<<10) /* PCM interface A Extra Data Strobe Enable */ #define PCM_FSINV (1<< 9) /* PCM interface frame synchronization polarity invert */ #define PCM_ICC_OFFSET (0) /* PCM interface Channel Inter Change control */ #define PCM_ICC_MASK (0xf< {1,0,3,2} */ #define GDMA_SWAPTYPE1 (1<<22) /* Original:{0,1,2,3} => {3,2,1,0} */ #define GDMA_ENTSIZMASK (3<<20) /* T-CAM Entry Size Mask */ #define GDMA_ENTSIZ32 (0<<20) /* T-CAM Entry Size 32 bits */ #define GDMA_ENTSIZ64 (1<<20) /* T-CAM Entry Size 64 bits */ #define GDMA_ENTSIZ128 (2<<20) /* T-CAM Entry Size 128 bits */ #define GDMA_ENTSIZ256 (3<<20) /* T-CAM Entry Size 256 bits */ /* Generic DMA Interrupt Mask Register */ #define GDMA_COMPIE (1<<31) /* Completed Interrupt Enable */ #if 0 /* phase out */ #define GDMA_SBUDRIE (1<<30) /* Source Block Under-run Interrupt Enable */ #define GDMA_DBUDRIE (1<<29) /* destination Block Under-run Interrupt Enable */ #endif #define GDMA_NEEDCPUIE (1<<28) /* Need-CPU Interrupt Enable */ /* Generic DMA Interrupt Status Register */ #define GDMA_COMPIP (1<<31) /* Completed Interrupt Status (write 1 to clear) */ #if 0 /* phase out */ #define GDMA_SBUDRIP (1<<30) /* Source Block Under-run Interrupt Status (write 1 to clear) */ #define GDMA_DBUDRIP (1<<29) /* destination Block Under-run Interrupt Status (write 1 to clear) */ #endif #define GDMA_NEEDCPUIP (1<<28) /* Need-CPU Interrupt Status (write 1 to clear) */ /* Generic DMA Source Block Length n. Register */ #define GDMA_LDB (1<<31) /* Last Data Block */ #define GDMA_BLKLENMASK (0x1fff) /* Block Length (valid value: from 1 to 8K-1 bytes) */ #if defined(CONFIG_RTL8186_KB) void rtl865x_startBooting_ledControl(void); void rtl865x_wireCompSolidBlue(void); void rtl865x_wireCompBlinkAmber(void); #endif //hyking:define for 8196C FIB test chip #if defined(CONFIG_RTL_8196C) #define RTL8196C_EEE_MAC #endif #define GIGA_P5_PHYID 0x16 #define BSP_REVR 0xB8000000 #define BSP_RTL8198_REVISION_A 0xC0000000 #define BSP_RTL8198_REVISION_B 0xC0000001 #define SYS_CLK_MAG 0xb8000010 #define SYS_SW_CLK_ENABLE 0x200 #define SYS_SW_RESET 0x800 #endif /* _ASICREGS_H */